Pin Description - Samsung M471B1G73AH0 Hardware User Manual

Unbuffered SODIMM

5. Pin Description

Pin Name
CK0, CK1 Clock Inputs, positive line
CK0, CK1 Clock Inputs, negative line
CKE0, CKE1 Clock Enables
RAS Row Address Strobe
CAS Column Address Strobe
WE Write Enable
S0, S1 Chip Selects
A0-A9, A11,
Address Inputs
A13-A15
A10/AP Address Input/Autoprecharge
A12/BC Address Input/Burst chop
BA0-BA2 SDRAM Bank Addresses
ODT0, ODT1 On-die termination control
SCL Serial Presence Detect (SPD) Clock Input
SDA SPD Data Input/Output
SA0-SA1 SPD Address
NOTE:
* The V and V pins are tied common to a single power-plane on these designs.
DD DDQ
datasheet
Description Number Pin Name
2 DQ0-DQ63 Data Input/Output
Data Masks/ Data strobes,
2 DM0-DM7
Termination data strobes
2 DQS0-DQS7 Data strobes
1 DQS0-DQS7 Data strobes complement
1 RESET Reset Pin
Logic Analyzer specific test pin (No connect
1 TEST
on SODIMM)
V
2 Core and I/O Power
DD
V
14 Ground
SS
V
REFDQ
1 Input/Output Reference
V
REFCA
V
1 SPD and Temp sensor Power
DDSPD
V
3 Termination Voltage
TT
2 NC Reserved for future use
1 Total
1
2
- 6 -
Rev. 1.0
DDR3 SDRAM
Description Number
64
8
8
8
1
1
18
52
2
1
2
3
204