Three-Phase Pwm Timing Unit Operation - Analog Devices ADSP-BF506F Hardware Reference Manual

Functional Description
+PWMTM/2
COUNT
PWM_AH
A
PWM_AL
2*PWMDT
PWM_AH
B
PWM_AL
Figure 14-5. Examples of Transitioning from Normal Modulation to
Full On Mode (A) or Full Off Mode (B)

Three-Phase PWM Timing Unit Operation

The internal operation of the PWM Controller is controlled by the
Three-Phase PWM Timing Unit, which is clocked at the system clock rate
with period t
SCLK
over one full PWM period is illustrated in
During the first half cycle (when the
register is cleared), the Three-Phase PWM Timing Unit decrements from
+PWMTM/2 to -PWMTM/2 using a two's complement count. Then the
14-22
-PWMTM/2
0
PWMCHA
1
. The operation of the Three-Phase PWM Timing Unit
ADSP-BF50x Blackfin Processor Hardware Reference
0
2*PWMDT
DEADTIME INSERTED HERE
Figure 14-6.
bit of the
PWM_PHASE
+PWMTM/2
PWM_STAT