Peripheral Dma - Analog Devices ADSP-BF506F Hardware Reference Manual

The 16-bit DMA core bus (DCB) connects the DMA controller to a dedi-
cated port of L1 memory. L1 memory has dedicated DMA ports featuring
special DMA buffers to decouple DMA operation. See Blackfin Processor
Programming Reference for a description of the L1 memory architecture.
The DCB bus operates at core clock (
troller's responsibility to translate DCB transfers to the system clock
( ) domain.
SCLK
The 16-bit DMA access bus (DAB) connects the DMA controller to the
on-chip peripherals. This bus operates at
The 16-bit DMA external bus (DEB) connects the DMA controller to the
EBIU port. This bus is used for all peripheral and memory DMA transfers
to and from external memories and devices. It operates at
Transferred data can be 8-, 16-, or 32-bits wide. The DMA controller,
however, connects only to 16-bit buses.
Memory DMA can pass data every SCLK cycle between L1 memory and
the EBIU. Transfers from L1 memory to L1 memory require two cycles, as
the DCB bus is used for both source and destination transfers. Similarly,
transfers between two off-chip devices require EBIU and DEB resources
twice. Peripheral DMA transfers can be performed every other SCLK
cycle.
For more details on DMA performance see
page 7-41.

Peripheral DMA

The DMA controller features 12 channels that perform transfers between
peripherals and on-chip or off-chip memories. The user has full control
over the mapping of DMA channels and peripherals. The default DMA
channel priority and mapping, shown in
changed by altering the 4-bit
ters for the peripheral DMA channels.
ADSP-BF50x Blackfin Processor Hardware Reference
Direct Memory Access
) frequency. It is the DMA con-
CCLK
frequency.
SCLK
"DMA Performance" on
Table 7-7 on page
field in the
PMAP DMAx_PERIPHERAL_MAP
frequency.
SCLK
7-105, can be
regis-
7-5