Bringing Internal Flash Memory Out Of Reset - Analog Devices ADSP-BF506F Hardware Reference Manual

Internal Flash Memory Programming Guidelines
• Hold (HT): the time between read-enable deassertion (
write-enable deassertion (
( )
AMS0
• Transition (TT): the time between a read access in the current
bank and a write access to the current bank or a read access to a dif-
ferent bank.
Each of these parameters can be programmed in terms of EBIU clock
cycles. In addition, there are minimum values for these parameters:
• ST  1 cycle
• RAT  1 cycle
• WAT  1 cycle
• HT  0 cycle
• TT  1 cycle

Bringing Internal Flash Memory Out of Reset

The pin of the internal flash memory device is controlled by bit 0 of the
RP
FLASH_CONTROL
enables the flash by bringing it out of reset.
Refer to ADSP-BF504, ADSP-BF504F, ADSP-BF506F Embedded Proces-
sor Data Sheet for the timing requirements needed to bring the internal
flash memory out of reset. A minimum time (listed in the data sheet)
should elapse before the signals
time should elapse before the
requirements may be met by inserting an appropriate number of delay
6-78
AWE
register. Setting bit 0 of the
,
W
signal is toggled again. These timing
RP
ADSP-BF50x Blackfin Processor Hardware Reference
) and the end of the memory cycle
FLASH_CONTROL
, , and are asserted, and a minimum
E G L
) or
ARE
register to 1