SPI Registers
register is cleared and an SPI transfer may be initiated (if
SPI_STAT
=
).
TIMOD
b#00
SPI Receive Data Buffer Register (SPI_RDBR)
Read Only
15 14 13 12 11 10
0
0
0
0
0
Figure 18-17. SPI Receive Data Buffer Register
SPI RDBR Shadow (SPI_SHADOW) Register
The SPI_SHADOW register is provided for use in debugging software.
This register is at a different address than the receive data buffer,
SPI_RDBR, but its contents are identical to that of SPI_RDBR. When a
software read of SPI_RDBR occurs, the RXS bit in SPI_STAT is cleared
and an SPI transfer may be initiated (if TIMOD = b#00 in SPI_CTL). No
such hardware action occurs when the SPI_SHADOW register is read.
The SPI_SHADOW register is read-only.
SPI RDBR Shadow Register (SPI_SHADOW)
Read Only
15 14 13 12 11 10
0
0
0
0
0
Figure 18-18. SPI RDBR Shadow Register
18-44
9
8
7
6
5
4
0
0
0
0
0
0
0
9
8
7
6
5
4
3
0
0
0
0
0
0
0
0
ADSP-BF50x Blackfin Processor Hardware Reference
3
2
1
0
0
0
0
0
Reset = 0x0000
Receive Data Buffer[15:0]
2
1
0
Reset = 0x0000
Reset = 0x0000
0
0
0
SPI_RDBR Shadow[15:0]
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