If enabled by the
an interrupt on the dedicated
the DMA controller. If the associated DMA channel is enabled, the
signal functions as a DMA request, otherwise the DMA controller simply
forwards it to the SIC interrupt controller. If no DMA channel is assigned
to the UART, the
receive and transmit interrupts to the UART status interrupt alternatively.
The state of the five-deep receiver buffer (including
monitored by the receiver FIFO count status (
register. The buffer's behavior is controlled by the receive FIFO interrupt
threshold (
RFIT
is set when the receive buffer holds two or more words. If
bit is set when the receive buffer holds four or more words. The
RFCS
bit is cleared by hardware when core or DMA read the
and when the buffer is flushed below the level of two (
(
=4). If the associated interrupt bit
RFIT
is reported when the
If errors are detected during reception, an interrupt can be requested to a
the status interrupt output. This status interrupt request goes directly to
the SIC interrupt controller. Status interrupt requests are enabled by the
bit in the
ELSI
detected. Every error has an indicating bit in the
• Overrun error (
• Parity error (
• Framing error/Invalid stop bit (
• Break indicator (
The sampling clock is 16 times faster than the bit clock. The receiver over
samples every bit 16 times and does a majority decision based on the mid
three samples. This improves immunity against noise and hazards on the
ADSP-BF50x Blackfin Processor Hardware Reference
bit in the
ERBFI
RXREQ
bit in the
EGLSI
) bit in the
UARTx_MCR
bit is set.
RFCS
register. The following error situations are
UARTx_IER_SET
bit)
OE
bit)
PE
bit)
BI
UART Port Controllers
register, the
UARTx_IER
output. This signal is routed through
register can redirect the
UARTx_GCTL
) bit in the
RFCS
register. If
RFIT
is enabled, status interrupt
ERFCI
UARTx_LSR
bit)
FE
flag requests
DR
RXREQ
) can be
UARTx_RBR
UARTx_MSR
is zero, the
RFCS
is set, the
RFIT
RFCS
register
UARTx_RBR
=0) or four
RFIT
register.
15-9
bit
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