Synchronous Burst Read Suspend - Analog Devices ADSP-BF506F Hardware Reference Manual

continuous burst read mode a wait state occurs when crossing the first 16-
word boundary. If the burst starting address is aligned to a 4-word page,
the wait state does not occur.
The signal can be configured to be active low or active high by set-
WAIT
ting in the configuration register. The
CR10
in synchronous burst read mode. In other modes,
(except for read array mode).

Synchronous Burst Read Suspend

A synchronous burst read operation can be suspended, freeing the data bus
for other higher priority devices. It can be suspended during the initial
access latency time (before data is output), or after the device has output
data. When the synchronous burst read operation is suspended, internal
array sensing continues and any previously latched internal data is
retained. A burst sequence can be suspended and resumed as often as
required as long as the operating conditions of the device are met.
A synchronous burst read operation is suspended when
current address has been latched (on a latch enable rising edge or on a
valid clock edge). The clock signal is then halted at
goes high.
When becomes low again and the clock signal restarts, the synchronous
G
burst read operation is resumed exactly where it stopped.
being gated by
WAIT
ance when goes high. Therefore, if two or more devices are connected to
G
the system's
READY
internal flash memory should not be directly connected to the system's
signal.
READY
ADSP-BF50x Blackfin Processor Hardware Reference
remains active and does not revert to high-imped-
E
signal, to prevent bus contention the
Internal Flash Memory
signal is meaningful only
WAIT
is always asserted
WAIT
is low and the
E
or at
V V
IH
signal of the
WAIT
, and
G
IL
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