Analog Devices ADSP-BF506F Hardware Reference Manual page 441

Figure 10-6. Example of Timers With Pulses Aligned to Asserting Edge
The
TOGGLE_HI
and deasserting edges of the output waveform produced. The phase
between the asserting edges of two timer outputs is programmable. The
effective state of the
active low and active high pulses, taken together, create two halves of a
symmetrical rectangular waveform. The effective waveform is active high
when
PULSE_HI
of the
TOGGLE_HI
= 1.
PERIOD_CNT
In mode, when
TOGGLE_HI
in the first, third, and all odd-numbered periods, and an active high pulse
is generated in the second, fourth, and all even-numbered periods. When
is cleared, an active high pulse is generated in the first, third,
PULSE_HI
and all odd-numbered periods, and an active low pulse is generated in the
second, fourth, and all even-numbered periods.
The deasserted state at the end of one period matches the asserted state at
the beginning of the next period, so the output waveform only transitions
when Count = Pulse Width. The net result is an output waveform pulse
that repeats every two counter periods and is centered around the end of
the first period (or the start of the second period).
ADSP-BF50x Blackfin Processor Hardware Reference
TOGGLE_HI = 0
PULSE_HI = 1
TMR0
ACTIVE
HIGH
TOGGLE_HI = 0
PULSE_HI = 1
TMR1
ACTIVE
HIGH
TOGGLE_HI = 0
PULSE_HI = 1 TMR2
ACTIVE
HIGH
TIMER
ENABLE
mode enables control of the timing of both the asserting
bit alternates every period. The adjacent
PULSE_HI
is set and active low when
bit has no effect unless the mode is
PULSE_HI
General-Purpose Timers
PERIOD 1
is cleared. The value
PULSE_HI
PWM_OUT
is set, an active low pulse is generated
and
10-17