Sport Receive Configuration (Sport_Rcr1 And Sport_Rcr2) Registers - Analog Devices ADSP-BF506F Hardware Reference Manual

SPORT Registers
• Late transmit frame sync. (
syncs (if set) or early frame syncs (if cleared).
• Clock drive/sample edge select. (
edge of the
ing internally generated frame syncs, and for sampling externally
generated frame syncs. If set, data and internally generated frame
syncs are driven on the falling edge, and externally generated frame
syncs are sampled on the rising edge. If cleared, data and internally
generated frame syncs are driven on the rising edge, and externally
generated frame syncs are sampled on the falling edge.
• TxSec enable. (
of the SPORT (if set).
• Stereo serial enable. (
ating mode of the SPORT (if set). By default this bit is cleared,
enabling normal clocking and frame sync.
• Left/Right order. (
transmitted first in stereo serial operating mode. By default this bit
is cleared, and the left channel is transmitted first.
SPORT Receive Configuration
(SPORT_RCR1 and SPORT_RCR2) Registers
The main control registers for the receive portion of each SPORT are the
receive configuration registers, SPORT_RCR1 and SPORT_RCR2,
shown in Figure 19-27
A SPORT is enabled for receive if bit 0 (
tion 1 register is set to 1. This bit is cleared during either a hard reset or a
soft reset, disabling all SPORT reception.
19-52
LATFS
signal the SPORT uses for driving data, for driv-
TCLKx
). This bit enables the transmit secondary side
TXSE
). This bit enables the stereo serial oper-
TSFSE
). If this bit is set, the right channel is
TRFST
and Figure 19-28.
ADSP-BF50x Blackfin Processor Hardware Reference
). This bit configures late frame
). This bit selects which
TCKFE
) of the receive configura-
RSPEN