Command Interface to Internal Flash Memory
Two bus write cycles are required to issue the block lock-down command:
• The first bus cycle sets up the block lock command.
• The second bus write cycle latches the block address.
The lock status can be monitored for each block using the read electronic
signature command. Locked-down blocks revert to the locked (and not
locked-down) state when the device is reset on power-down.
on page 6-41
shows the lock status after issuing a block lock-down com-
mand. Refer to
and
Figure 6-9 on page 6-64
and pseudo code for using the lock-down command.
Table 6-5. Standard Commands
Commands
Read Array
Read Status Register
Read Electronic Signature
Read CFI Query
Clear Status Register
Block Erase
Program
Program/Erase Suspend
Program/Erase Resume
Protection Register Program 2
Set Configuration Register
6-16
"Block Locking" on page 6-38
and
Listing 6-5 on page 6-64
Cycles
Bus Operations
1st Cycle
Op.
1+
Write
1+
Write
1+
Write
1+
Write
1
Write
2
Write
2
Write
1
Write
1
Write
Write
2
Write
ADSP-BF50x Blackfin Processor Hardware Reference
for a detailed explanation,
1
2nd Cycle
Add
Data
Op.
BKA
0xFF
Read
BKA
0x70
Read
BKA
0x90
Read
BKA
0x98
Read
X
0x50
BKA or
0x20
Write
3
BA
BKA or
0x40or
Write
3
0x10
WA
X
0xB0
X
0xD0
PRA
0xC0
Write
CRD
0x60
Write
Table 6-15
for a flowchart
Add
Data
WA
RD
2
SRD
BKA
2
ESD
BKA
2
QD
BKA
BA
0xD0
WA
PD
PRA
PRD
CRD
0x03
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