Repeated Start Condition; Transmit/Receive Repeated Start Sequence - Analog Devices ADSP-BF506F Hardware Reference Manual

Table 16-4 shows what the interaction between the TWI controller and
the processor might look like using this example.
Table 16-4. Master Mode Receive Setup Interaction
TWI Controller Master
Interrupt: RCVFULL – Receive buffer is full.
...
Interrupt: MCOMP – Master transfer com-
plete.

Repeated Start Condition

In general, a repeated start condition is the absence of a stop condition
between two transfers. The two transfers can be of any direction type.
Examples include a transmit followed by a receive, or a receive followed by
a transmit. The following sections guide the programmer in developing a
service routine.

Transmit/Receive Repeated Start Sequence

Figure 16-7 shows a repeated start data transmit followed by a data receive
sequence.
7-BIT ADDRESS R/W ACK
S
XMTSERV INTERRUPT
SHADING INDICATES SLAVE HAS THE BUS
Figure 16-7. Transmit/Receive Data Repeated Start
ADSP-BF50x Blackfin Processor Hardware Reference
8-BIT DATA ACK S 7-BIT ADDRESS
MCOMP INTERRUPT
Two-Wire Interface Controller
Processor
Read receive FIFO buffer.
Acknowledge: Clear interrupt source bits.
...
Acknowledge: Clear interrupt source bits.
Read receive FIFO buffer.
ACK
R/W
RCVSERV INTERRUPT
8-BIT DATA ACK P
MCOMP INTERRUPT
16-15