Programming Examples; Clearing Interrupt Requests - Analog Devices ADSP-BF506F Hardware Reference Manual

peripheral interrupt IDs are mapped to the
ticular processor.

Programming Examples

The following section provides an example for servicing interrupt
requests.

Clearing Interrupt Requests

When the processor services a core event it automatically clears the
requesting bit in the
interrupt service routine. It is important to understand that the SIC con-
troller does not provide any interrupt acknowledgment feedback
mechanism from the CEC controller back to the peripherals. Although
the bits clear in the same way when a peripheral interrupt is serviced,
ILAT
the signalling peripheral does not release its level-sensitive request until it
is explicitly instructed by software. If however, the peripheral keeps
requesting, the respective
routine is invoked again as soon as its first run terminates by an RTI
instruction.
Every software routine that services peripheral interrupts must clear the
signalling interrupt request in the respective peripheral. The individual
peripherals provide customized mechanisms for how to clear interrupt
requests. Receive interrupts, for example, are cleared when received data is
read from the respective buffers. Transmit requests typically clear when
software (or DMA) writes new data into the transmit buffers. These
implicit acknowledge mechanisms avoid the need for cycle-consuming
software handshakes in streaming interfaces. Other peripherals such as
timers, GPIOs, and error requests require explicit acknowledge instruc-
tions, which are typically performed by efficient W1C (write-1-to-clear)
operations.
ADSP-BF50x Blackfin Processor Hardware Reference
register and no further action is required by the
ILAT
bit is set again immediately and the service
ILAT
System Interrupts
register(s) for this par-
SIC_IWR
4-13