Analog Devices ADSP-BF506F Hardware Reference Manual page 907

SPORT Transmit Configuration 2 Register (SPORT_TCR2)
15 14 13 12 11 10
0 0 0
TRFST (Left/Right Order)
0 - Left stereo channel first
1 - Right stereo channel first
TSFSE (Transmit Stereo
Frame Sync Enable)
0 - Normal mode
1 - Frame sync becomes L/R clock
Figure 19-26. SPORT Transmit Configuration 2 Register
Additional information for the
figuration register bits includes:
• Transmit enable (
enabled to transmit (if set) or disabled (if cleared).
Setting
rupt, indicating that the TX data register is empty and needs to be
filled. This is normally desirable because it allows centralization of
the transmit data write code in the TX interrupt service routine
(ISR). For this reason, the code should initialize the ISR and be
ready to service TX interrupts before setting
Similarly, if DMA transfers are used, DMA control should be con-
figured correctly before setting
registers before setting
Clearing
frame sync pins; it also shuts down the internal SPORT circuitry.
In low power applications, battery life can be extended by clearing
whenever the SPORT is not in use.
TSPEN
ADSP-BF50x Blackfin Processor Hardware Reference
9 8 7 6
0 0 0 0 0 0 0
SPORT_TCR1
). This bit selects whether the SPORT is
TSPEN
causes an immediate assertion of a SPORT TX inter-
TSPEN
TSPEN
causes the SPORT to stop driving data,
TSPEN
5 4 3 2 1 0
Reset = 0x0000
0 0 0 0 0 0
SLEN[4:0] (SPORT Word
Length)
00000 - Illegal value
00001 - Illegal value
Serial word length is value in
this field plus 1
TXSE (TxSEC Enable)
0 - Secondary side disabled
1 - Secondary side enabled
and
SPORT_TCR2
. Set all DMA control
TSPEN
.
SPORT Controller
transmit con-
.
TSPEN
, and
TSCLK
19-49