Master Mode Clock Setup - Analog Devices ADSP-BF506F Hardware Reference Manual

Functional Description
3. Program
interrupt sources. As an example, programming the value 0x000F
results in an interrupt output to the processor in the event that a
valid address match is detected, a valid slave transfer completes, a
slave transfer has an error, a subsequent transfer has begun yet the
previous transfer has not been serviced.
4. Program
mode operation. As an example, programming the value 0x0005
enables slave mode operation, requires 7-bit addressing, and indi-
cates that data in the transmit FIFO buffer is intended for slave
mode transmission.
Table 16-2 shows what the interaction between the TWI controller and
the processor might look like using this example.
Table 16-2. Slave Mode Setup Interaction
TWI Controller Master
Interrupt: SINIT – Slave transfer in progress.
Interrupt: RCVFULL – Receive buffer is full.
...
Interrupt: SCOMP – Slave transfer complete.

Master Mode Clock Setup

Master mode operation is set up and executed on a per-transfer basis. An
example of programming steps for a receive and for a transmit are given
separately in following sections. The clock setup programming step listed
here is common to both transfer types.
• Program
clock low duration.
16-12
. Enable bits are associated with the desired
TWI_INT_MASK
. Ultimately this prepares and enables slave
TWI_SLAVE_CTL
. This defines the clock high duration and
TWI_CLKDIV
ADSP-BF50x Blackfin Processor Hardware Reference
Processor
Acknowledge: Clear interrupt source bits.
Read receive FIFO buffer.
Acknowledge: Clear interrupt source bits.
...
Read receive FIFO buffer.
Acknowledge: Clear interrupt source bits.