Rsi Data Timer Register (Rsi_Data_Timer) - Analog Devices ADSP-BF506F Hardware Reference Manual

Table 21-16. RSI Response Registers Content
Response Register
RSI_RESPONSE0
RSI_RESPONSE1
RSI_RESPONSE2
RSI_RESPONSE3
1 Bits 31:1 of the long response are stored in bits 30:0 of the RSI_RESPONSE3 register.
Bit 31 of the RSI_RESPONSE3 register is not used and is always zero.

RSI Data Timer Register (RSI_DATA_TIMER)

The
RSI_DATA_TIMER
period (
RSI_CLK
ister, and starts to decrement when the data path state machine enters the
WAIT_R or the BUSY states. If the timer decrements to zero while the
data path state machine is still in either of these two states, the
flag of the
DAT_TIMEOUT
and the
RSI_DATA_LGTH
data transfer via the
RSI Data Timer Register (RSI_DATA_TIMER)
Read
31 30 29 28 27 26
0xFFC0 3824
0
0
Data Timeout Period [31:16]
15 14 13 12 11 10
0
Data Timeout Period [15:0]
Figure 21-12. RSI Data Timer Register
ADSP-BF50x Blackfin Processor Hardware Reference
Short Response
Response bits [31:0]
Not used
Not used
Not used
register contains a 32-bit value for the data timeout
cycles). An internal counter loads the value from this reg-
RSI_STATUS
registers must both be written to prior to starting a
RSI_DATA_CONTROL
25 24 23 22 21 20 19 18 17 16
0 0 0
0 0 0 0
9 8 7
0 0 0 0 0 0 0 0
Removable Storage Interface
Long Response
Response bits [127:96]
Response bits [95:64]
Response bits [63:32]
Response bits [31:1]
register is set. The
register.
0 0 0 0 0 0 0
6 5 4 3 2 1 0
0 0 0 0 0 0 0
1
RSI_DATA_TIMER
Reset = 0x0000 0000
21-61