Analog Devices ADSP-BF506F Hardware Reference Manual page 130

Unique Information for the ADSP-BF50x Processor
Table 4-3. Peripheral Interrupt Events (Part 1) (Cont'd)
Peripheral Bit Position for
ID Number SIC_ISR0,
SIC_IMASK0,
SIC_IWR0
7 Bit 7
6 Bit 6
5 Bit 5
4 Bit 4
3 Bit 3
2 Bit 2
1 Bit 1
0 Bit 0
Table 4-4. Peripheral Interrupt Events (Part 2)
Peripheral Bit Position for
ID Number SIC_ISR1,
SIC_IMASK1,
SIC_IWR1
63 Bit 31
62 Bit 30
61 Bit 29
60 Bit 28
59 Bit 27
58 Bit 26
57 Bit 25
56 Bit 24
55 Bit 23
54 Bit 22
53 Bit 21
4-20
SIC_IAR3-0 Interrupt Source
SIC_IAR0[31:28] SPI0 Status
SIC_IAR0[27:24] UART1 Status
SIC_IAR0[23:20] UART0 Status
SIC_IAR0[19:16] SPORT1 Status
SIC_IAR0[15:12] SPORT0 Status
SIC_IAR0[11:8] PPI Status
SIC_IAR0[7:4] DMA Error (generic)
SIC_IAR0[3:0] PLL Wakeup Interrupt
SIC_IAR7–4 Interrupt Source
SIC_IAR7[31:28] Reserved
SIC_IAR7[27:24] Reserved
SIC_IAR7[23:20] Reserved
SIC_IAR7[19:16] Reserved
SIC_IAR7[15:12] Reserved
SIC_IAR7[11:8] Reserved
SIC_IAR7[7:4] Reserved
SIC_IAR7[3:0] Reserved
SIC_IAR6[31:28] RSI Mask 1 Interrupt
SIC_IAR6[27:24] PWM1 Sync Interrupt
SIC_IAR6[23:20] PWM1 Trip Interrupt
ADSP-BF50x Blackfin Processor Hardware Reference
Default
Mapping
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
Default
Mapping
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG10
IVG10
IVG10