Master Mode Dma Operation - Analog Devices ADSP-BF506F Hardware Reference Manual

Programming Model
software performs a dummy read from the
first transfer. If the first transfer is used for data transmission, software
should write the value to be transmitted into the
performing the dummy read. If the transmitted value is arbitrary, it is
good practice to set the
transmitted rather than random values. When receiving the last word of
an SPI stream, software should ensure that the read from the
register does not initiate another transfer. It is recommended that the SPI
port be disabled before the final
register is not sufficient, as it does not clear the interrupt
SPI_SHADOW
request.
In master mode with the
required slave select signal before starting the transaction. After all data
has been transferred, software typically releases the slave select again. If the
SPI slave device requires the slave select line to be asserted for the
complete transfer, this can be done in the SPI interrupt service routine
only when operating in
= or
TIMOD b#01
is still in progress.

Master Mode DMA Operation

When enabled as a master with the DMA engine configured to transmit or
receive data, the SPI interface operates as follows.
1. The core writes to the appropriate port register(s) to properly con-
figure the SPI for master mode operation. The appropriate pins can
be configured for SPI use as slave-select outputs.
2. The processor core writes to the appropriate DMA registers to
enable the SPI DMA channel and to configure the necessary work
units, access direction, word count, and so on. For more informa-
tion, see the Direct Memory Access chapter.
18-24
bit in the
SZ
SPI_RDBR
bit set, software should manually assert the
CPHA
=
TIMOD b#00
= , the interrupt is requested while the transfer
TIMOD b#11
ADSP-BF50x Blackfin Processor Hardware Reference
register to initiate the
SPI_RDBR
SPI_TDBR
register to ensure zero data is
SPI_CTL
read access. Reading the
or = mode. With
TIMOD b#10
register before
SPI_RDBR