Analog Devices ADSP-BF506F Hardware Reference Manual page 894

Adsp-bf50x blackfin processor
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Functional Description
framing mode. Continuous operation is restricted to word sizes of 4 or
longer (
SLEN
When
= 1 or
LATFS
alternate mode of operation. In this mode, the first bit of the transmit data
word is available and the first bit of the receive data word is sampled in the
same serial clock cycle that the frame sync is asserted. In multichannel
operation, this is the case when frame delay is 0. Receive data bits are sam-
pled by serial clock edges, but the frame sync signal is only checked during
the first bit of each word. Internally generated frame syncs remain asserted
for the entire length of the data word in late framing mode. Externally
generated frame syncs are only checked during the first bit.
Figure 19-12
illustrates the two modes of frame signal timing. In
summary:
• For the
ters:
LATFS
= 1 for late frame syncs.
LARFS
• For early framing, the frame sync precedes data by one cycle. For
late framing, the frame sync is checked on the first bit only.
• Data is transmitted MSB first (
first (
TLSBIT
• Frame sync and clock are generated internally or externally.
See
"Timing Examples" on page 19-39
19-36
3).
= 1, late frame syncs are configured; this is the
LARFS
or
bits of the
LATFS
LARFS
= 0 or
= 0 for early frame syncs,
LARFS
= 1 or
RLSBIT
ADSP-BF50x Blackfin Processor Hardware Reference
SPORT_TCR1
= 0 or
TLSBIT
= 1).
for more examples.
or
regis-
SPORT_RCR1
= 1 or
LATFS
= 0) or LSB
RLSBIT

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