Descriptor List Mode; Descriptor Array Mode; Variable Descriptor Size - Analog Devices ADSP-BF506F Hardware Reference Manual

Descriptor List Mode

Descriptor list mode is selected by setting the FLOW bit field in the DMA
channel's DMAx_CONFIG register to either 0x6 (small descriptor mode)
or 0x7 (large descriptor mode). In either of these modes multiple descrip-
tors form a chained list. Every descriptor contains a pointer to the next
descriptor. When the descriptor is fetched, this pointer value is loaded
into the DMAx_NEXT_DESC_PTR register of the DMA channel. In
large descriptor mode this pointer is 32 bits wide. Therefore, the next
descriptor may reside in any address space accessible through the DCB
and DEB buses. In small descriptor mode this pointer is just 16 bits wide.
For this reason, the next descriptor must reside in the same 64K byte
address space as the first one because the upper 16 bits of the
DMAx_NEXT_DESC_PTR register are not updated.
Descriptor list modes are started by writing first to the
DMAx_NEXT_DESC_PTR

Descriptor Array Mode

Descriptor array mode is selected by setting the FLOW bit field in the
DMA channel's DMAx_CONFIG register to 0x4. In this mode, the
descriptors do not contain further descriptor pointers. The initial
DMAx_CURR_DESC_PTR value is written by software. It points to an
array of descriptors. The individual descriptors are assumed to reside next
to each other and, therefore, their addresses are known.

Variable Descriptor Size

In any descriptor-based mode the
specifies how many 16-bit words of the next descriptor need to be loaded
on the next fetch. In descriptor-based operation,
non-zero. The descriptor size can be any value from one entry (the lower
16 bits of
DMAx_START_ADDR
ters). Table 7-1
ADSP-BF50x Blackfin Processor Hardware Reference
register and then to the
NDSIZE
only) to nine entries (all the DMA parame-
illustrates how a descriptor must be structured in
Direct Memory Access
register.
DMAx_CONFIG
field in the configuration word
must be
NDSIZE
7-15