Spi Slave Select Enable Output Signals - Analog Devices ADSP-BF506F Hardware Reference Manual

SCK
(CPOL = 1)
SPISS
(TO SLAVE)
Figure 18-3. SPI Timing
For a master device with
for at least one-half the
always be equal to one-half the

SPI Slave Select Enable Output Signals

When operating in master mode, Blackfin processors may use any GPIO
pin to enable individual SPI slave devices by software. In addition, the SPI
module provides hardware support to generate up to seven slave select
enable signals automatically (depending upon the configuration of the
specific processor). See
These signals are always active low in the SPI protocol. Since the respec-
tive pins are not driven during reset, it is recommended to pull them up
by a resistor.
If enabled as a master, the SPI uses the
eral-purpose port pins to be used as individual slave select lines. Before
manipulating this register, the port pins that are to be used as SPI
slave-select outputs must first be configured as such. To work as SPI out-
put pins, the port pins must be enabled for use by SPI in the appropriate
register.
PORT_MUX
ADSP-BF50x Blackfin Processor Hardware Reference
SPI-Compatible Port Controller
= 0, the slave select output is inactive (high)
CPHA
period. In this case, T1 and T2 will each
SCK
period.
SCK
Figure 18-14 on page 18-38
SPI_FLG
T1 T2
T3
T4
for details.
register to enable gen-
18-7