Gate Drive Unit; High-Frequency Chopping - Analog Devices ADSP-BF506F Hardware Reference Manual

Gate Drive Unit

The Gate Drive Unit is described in the following sections:
•

"High-Frequency Chopping"

• "PWM Polarity Control" on page 14-30
High-Frequency Chopping
The Gate Drive Unit of the PWM Controller simplifies the design of
isolated gate drive circuits for PWM inverters. If a transformer-coupled
power device gate drive amplifier is used, the active PWM signal must be
chopped at a high frequency. The 10-bit read/write
allows you to specify this high-frequency chopping mode.
Chopped active PWM signals may be required for high-side drivers only,
for low-side drivers only, or for both high-side and low-side switches.
Therefore, independent control of this mode for both high- and low-side
switches is included with two separate control bits (
the register.
PWM_GATE
Typical PWM output signals with high-frequency chopping enabled on
both high- and low-side signals are shown in
high-side PWM outputs (
bit of the
PWM_GATE
and ) is enabled by setting the
CL
high-frequency chopping frequency is controlled by the 8-bit word placed
in bits 0 to 7 (
quency carrier is:
ADSP-BF50x Blackfin Processor Hardware Reference
, , and
AH BH
register; chopping the low-side PWM outputs (
) of the
GDCLK PWM_GATE
  
=
T 4 GDCLK
chop
Figure
) is enabled by setting the
CH
bit of the
CHOPLO PWMGATE
register. The period of this high-fre-
  t 
+
1
SCLK
PWM Controller
register
PWM_GATE
and
CHOPHI CHOPLO
14-8. Chopping the
CHOPHI
,
AL
register. The
14-29
) in
,
BL