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a STOP mode DMA. Thus, the normal completion interrupt is sup-
pressed. Rather, the
and triggers the DMA interrupt. If both,
interrupts are requested at the end of a STOP mode DMA.
The
UARTx_IIR
Signalling interrupt sources can be identified by interrogating
UARTx_LSR
UARTx_DLL and UARTx_DLH Registers
The two 8-bit clock divisor latch registers (
build a 16-bit clock divisor value. They divide the system clock
to the bit clock. These registers are shown in
UART Divisor Latch Low Byte Registers (UARTx_DLL)
15 14 13 12 11 10
For memory-
0
0
mapped
addresses,
see
Table
15-13.
UART Divisor Latch High Byte Registers (UARTx_DLH)
15 14 13 12 11 10
For memory-
0
0
mapped
addresses,
see
Table
15-14.
Figure 15-16. UART Divisor Latch Registers
ADSP-BF50x Blackfin Processor Hardware Reference
event is signalled through the DMA controller
TEMT
registers are not present on this implementation.
and
UARTx_MSR
9
8
7
6
0
0
0
0
0
0
0
0
9
8
7
6
0
0
0
0
0
0
0
0
UART Port Controllers
and
DI_EN
status registers.
UARTx_DLH
Figure
5
4
3
2
1
0
Reset = 0x0001
0
0
0
0
0
0
Divisor Latch Low Byte[7:0]
5
4
3
2
1
0
Reset = 0x0000
0
0
0
0
0
0
Divisor Latch High Byte[15:8]
are set, two
ETDPTI
and
)
UARTx_DLL
down
SCLK
15-16.
15-43
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