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Analog Devices ADSP-BF506F Hardware Reference Manual

Adsp-bf50x blackfin processor

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ADSP-BF50x Blackfin

Processor

Hardware Reference

Revision 1.2, February 2013

Part Number

82-100101-01

Analog Devices, Inc.

a

One Technology Way

Norwood, Mass. 02062-9106

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Page 1: Hardware Reference
® ADSP-BF50x Blackfin Processor Hardware Reference Revision 1.2, February 2013 Part Number 82-100101-01 Analog Devices, Inc. One Technology Way Norwood, Mass. 02062-9106...
Page 2: Copyright Information
Analog Devices, Inc. Printed in the USA. Disclaimer Analog Devices, Inc. reserves the right to change this product without prior notice. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use;...
Page 3: Table Of Contents
Manual Contents ................lii What’s New in This Manual ............lv Technical Support ................lvi Supported Processors ..............lviiii Product Information ..............lviiii Analog Devices Web Site ............lviiii EngineerZone ................lix Notation Conventions ..............lx Register Diagram Conventions ............lxi INTRODUCTION General Description of Processor ...........
Page 4 Contents Memory Architecture ..............1-4 Internal Memory ..............1-6 External Memory ..............1-6 I/O Memory Space ..............1-7 DMA Support ................1-8 General-Purpose I/O (GPIO) ............1-9 Two-Wire Interface ..............1-10 RSI Interface ................1-11 General-Purpose (GP) Counter ........... 1-12 3-Phase PWM Unit ..............
Page 5 Contents Deep Sleep Operating Mode—Maximum Dynamic Power Savings ................1-26 Hibernate State—Maximum Static Power Savings ....1-26 Instruction Set Description ............1-27 Development Tools ..............1-28 MEMORY Memory Architecture ..............2-1 L1 Instruction SRAM ..............2-2 L1 Data SRAM ................2-3 L1 Data Cache ................
Page 6 Contents DMA Access Bus (DAB), DMA Core Bus (DCB), DMA External Bus (DEB) .............. 3-7 DAB, DCB, and DEB Arbitration ........3-7 DAB Bus Agents (Masters) ..........3-9 DAB, DCB, and DEB Performance ........3-9 External Access Bus (EAB) ............ 3-10 Arbitration of the External Bus ..........
Page 7 Contents Programming Examples ............... 4-13 Clearing Interrupt Requests ........... 4-13 Unique Information for the ADSP-BF50x Processor ....4-15 Interfaces ................4-15 System Peripheral Interrupts ..........4-18 EXTERNAL BUS INTERFACE UNIT EBIU Overview ................5-1 Block Diagram ................ 5-3 Internal Memory Interfaces ............5-4 Registers ..................
Page 8 Contents INTERNAL FLASH MEMORY Overview ..................6-1 Command Interface to Internal Flash Memory ......6-6 Command Interface – Standard Commands ......6-7 Read Array Command ............6-7 Read Status Register Command ......... 6-8 Read Electronic Signature Command ......... 6-8 Read CFI Query Command ..........6-9 Clear Status Register Command .........
Page 9 Contents Program Suspend Status Bit (SR2) ........6-22 Block Protection Status Bit (SR1) ........6-22 Bank Write Status Bit (SR0) ..........6-22 Configuration Register ............6-24 Read Select Bit (CR15) ............ 6-24 X Latency Bits (CR13-CR11) ........... 6-25 Wait Polarity Bit (CR10) ..........6-25 Data Output Configuration Bit (CR9) ......
Page 10 Contents Block Locking ..............6-38 Reading a Block’s Lock Status .......... 6-39 Locked State ..............6-39 Unlocked State ..............6-39 Lock-Down State ............. 6-40 Locking Operations During Erase Suspend ....... 6-40 Block Address Table ..............6-42 Common Flash Interface ............6-45 Flowcharts and Pseudo Codes ............
Page 11 Contents Internal Flash Memory Control Registers ........6-88 Internal Flash Memory Control (FLASH_CONTROL) Register ................6-88 Internal Flash Memory Control Set (FLASH_CONTROL_SET) Register ........6-91 Internal Flash Memory Control Clear (FLASH_CONTROL_CLEAR) Register ......6-91 DIRECT MEMORY ACCESS Specific Information for the ADSP-BF50x ........7-1 Overview and Features ..............
Page 12 Contents Variable Descriptor Size ............ 7-15 Mixing Flow Modes ............7-17 Functional Description ............... 7-17 DMA Operation Flow ............7-17 DMA Startup ..............7-17 DMA Refresh ..............7-23 Work Unit Transitions ............7-25 DMA Transmit and MDMA Source ......7-26 DMA Receive ...............
Page 13 Contents DMA Performance ..............7-41 DMA Throughput ............7-42 Memory DMA Timing Details .......... 7-45 Static Channel Prioritization ..........7-45 Temporary DMA Urgency ..........7-45 Memory DMA Priority and Scheduling ......7-47 Traffic Control ..............7-49 Programming Model ..............7-51 Synchronization of Software and DMA ........
Page 14 Contents DMA Start Address Registers (DMAx_START_ADDR/MDMA_yy_START_ADDR) . 7-75 DMA Current Address Registers (DMAx_CURR_ADDR/MDMA_yy_CURR_ADDR) ... 7-76 DMA Inner Loop Count Registers (DMAx_X_COUNT/MDMA_yy_X_COUNT) ..... 7-76 DMA Current Inner Loop Count Registers (DMAx_CURR_X_COUNT /MDMA_yy_CURR_X_COUNT) ........ 7-77 DMA Inner Loop Address Increment Registers (DMAx_X_MODIFY/MDMA_yy_X_MODIFY) ... 7-78 DMA Outer Loop Count Registers (DMAx_Y_COUNT/MDMA_yy_Y_COUNT) .....
Page 15 Contents Handshake MDMA Current Block Count Registers (HMDMAx_BCOUNT) ..........7-86 Handshake MDMA Current Edge Count Registers (HMDMAx_ECOUNT) ..........7-87 Handshake MDMA Initial Edge Count Registers (HMDMAx_ECINIT) ........... 7-88 Handshake MDMA Edge Count Urgent Registers (HMDMAx_ECURGENT) ..........7-88 Handshake MDMA Edge Count Overflow Interrupt Registers (HMDMAx_ECOVERFLOW) ......
Page 16 Contents Dynamic Power Management Controller ........8-7 Operating Modes ..............8-8 Dynamic Power Management Controller States ......8-8 Full-On Mode ..............8-8 Active Mode ............... 8-9 Sleep Mode ................ 8-9 Deep Sleep Mode ............. 8-10 Hibernate State ..............8-11 Operating Mode Transitions ..........8-11 Programming Operating Mode Transitions ......
Page 17 Contents Programming Examples ............... 8-29 Full-on Mode to Active Mode and Back ......... 8-31 Transition to Sleep Mode or Deep Sleep Mode ....... 8-32 Set Wakeup Events and Enter Hibernate State ......8-34 Perform a System Reset or Soft-Reset ........8-36 In Full-on Mode, Change VCO Frequency, Core Clock Frequency, and System Clock Frequency ......
Page 18 Contents Internal Interfaces ..............9-9 GP Timer Interaction With Other Blocks ......9-10 Buffered CLKIN (CLKBUF) ......... 9-10 GP Counter ..............9-10 PPI ................9-10 UART ................9-10 SPORT ................ 9-11 ACM ................9-11 Performance/Throughput ............9-12 Description of Operation ............9-12 Operation ................
Page 19 Contents GPIO Clear Registers (PORTxIO_CLEAR) ......9-32 GPIO Toggle Registers (PORTxIO_TOGGLE) ...... 9-33 GPIO Polarity Registers (PORTxIO_POLAR) ....... 9-33 Interrupt Sensitivity Registers (PORTxIO_EDGE) ....9-34 GPIO Set on Both Edges Registers (PORTxIO_BOTH) ..9-34 GPIO Mask Interrupt Registers (PORTxIO_MASKA/B) ..9-35 GPIO Mask Interrupt Set Registers (PORTxIO_MASKA/B_SET) ..........
Page 20 Contents Pulse Width Modulation Waveform Generation ....10-14 PULSE_HI Toggle Mode ..........10-16 Externally Clocked PWM_OUT ........10-21 Using PWM_OUT Mode With the PPI ......10-21 Stopping the Timer in PWM_OUT Mode ...... 10-22 Pulse Width Count and Capture (WDTH_CAP) Mode ..10-24 Autobaud Mode ..............
Page 21 Contents Overview and Features ..............11-1 Timer Overview ................11-2 External Interfaces ..............11-2 Internal Interfaces ..............11-3 Description of Operation ............11-3 Interrupt Processing ............... 11-3 Core Timer Registers ..............11-4 Core Timer Control Register (TCNTL) ......... 11-5 Core Timer Count Register (TCOUNT) ........ 11-5 Core Timer Period Register (TPERIOD) ........
Page 22 Contents Programming Examples .............. 12-8 Unique Information for the ADSP-BF50x Processor ....12-11 GENERAL-PURPOSE COUNTER Specific Information for the ADSP-BF50x ........13-1 Overview ..................13-2 Features ..................13-2 Interface Overview ..............13-3 Description of Operation ............13-4 Quadrature Encoder Mode ............ 13-4 Binary Encoder Mode ............
Page 23 Contents Capturing Timing Information ..........13-14 Capturing Time Interval Between Successive Counter Events ..........13-14 Capturing Counter Interval and CNT_COUNTER Read Timing ........13-15 Programming Model ..............13-18 Registers ................... 13-18 Counter Module Register Overview ........13-18 Counter Configuration Register (CNT_CONFIG) ....13-19 Counter Interrupt Mask Register (CNT_IMASK) ....
Page 24 Contents PWM Switching Dead Time (PWM_DT) Register ....14-12 PWM Operating Mode (PWM_CTRL and PWM_STAT) Registers ................14-13 PWM Duty Cycle (PWM_CHA, PWM_CHB, and PWM_CHC) Registers ... 14-14 Special Consideration for PWM Operation in Over-Modulation ............. 14-20 Three-Phase PWM Timing Unit Operation ......14-22 Effective PWM Accuracy .............
Page 25 Contents PWM Registers ................. 14-37 PWM Control (PWM_CTRL) Register ....... 14-38 PWM Status (PWM_STAT) Register ........14-40 PWM Period (PWM_TM) Register ........14-41 PWM Dead Time (PWM_DT) Register ....... 14-42 PWM Chopping Control (PWM_GATE) Register ....14-42 PWM Channel A, B, C Duty Control (PWM_CHA, PWM_CHB, PWM_CHC) Registers ..
Page 26 Contents UART Receive Operation ............15-8 Hardware Flow Control ............15-10 IrDA Transmit Operation ............ 15-13 IrDA Receive Operation ............15-14 Interrupt Processing ............15-16 Bit Rate Generation ............15-18 Autobaud Detection ............15-20 Programming Model ..............15-22 Non-DMA Mode ..............15-22 DMA Mode ................
Page 27 Contents Overview ..................16-2 Interface Overview ..............16-3 External Interface ..............16-3 Serial Clock Signal (SCL) ..........16-4 Serial Data Signal (SDA) ........... 16-4 TWI Pins ................16-5 Internal Interfaces ..............16-5 Description of Operation ............16-6 TWI Transfer Protocols ............16-6 Clock Generation and Synchronization ......
Page 28 Contents Clock Stretching ............. 16-18 Clock Stretching During FIFO Underflow ...... 16-18 Clock Stretching During FIFO Overflow ......16-20 Clock Stretching During Repeated Start Condition ..16-21 Programming Model ..............16-23 Register Descriptions ..............16-25 TWI CONTROL Register (TWI_CONTROL) ....16-25 SCL Clock Divider Register (TWI_CLKDIV) .....
Page 29 Contents TWI FIFO Receive Data Single Byte Register (TWI_RCV_DATA8) .......... 16-48 TWI FIFO Receive Data Double Byte Register (TWI_RCV_DATA16) ........16-48 Programming Examples ............. 16-50 Master Mode Setup ............. 16-50 Slave Mode Setup ..............16-55 Electrical Specifications ............. 16-61 Unique Information for the ADSP-BF50x Processor ....16-61 CAN MODULE Overview ..................
Page 30 Contents Receive Operation ............... 17-15 Data Acceptance Filter ............ 17-18 Remote Frame Handling ..........17-19 Watchdog Mode ............. 17-19 Time Stamps ............... 17-20 Temporarily Disabling Mailboxes ......... 17-21 Functional Operation ............... 17-22 CAN Interrupts ..............17-22 Mailbox Interrupts ............17-23 Global CAN Status Interrupt ..........
Page 31 Contents CAN Register Definitions ............17-39 Global CAN Registers ............17-43 CAN_CONTROL Register ..........17-43 CAN_STATUS Register ..........17-44 CAN_DEBUG Register ..........17-45 CAN_CLOCK Register ........... 17-45 CAN_TIMING Register ..........17-46 CAN_INTR Register ............17-46 CAN_GIM Register ............17-47 CAN_GIS Register ............17-47 CAN_GIF Register ............
Page 32 Contents CAN_TRSx Registers ............. 17-73 CAN_TRRx Registers ............. 17-74 CAN_AAx Register ............17-75 CAN_TAx Register ............17-76 CAN_MBTD Register ............ 17-77 CAN_RFHx Registers ............. 17-77 CAN_MBIMx Registers ..........17-78 CAN_MBTIFx Registers ..........17-79 CAN_MBRIFx Registers ..........17-80 Universal Counter Registers ..........17-82 CAN_UCCNF Register ..........
Page 33 Contents Features ..................18-2 Interface Overview ..............18-3 External Interface ..............18-4 SPI Clock Signal (SCK) ............. 18-5 Master-Out, Slave-In (MOSI) Signal ......... 18-5 Master-In, Slave-Out (MISO) Signal ......... 18-5 SPI Slave Select Input Signal (SPISS) ......... 18-6 SPI Slave Select Enable Output Signals ......18-7 Slave Select Inputs .............
Page 34 Contents Programming Model ..............18-22 Beginning and Ending an SPI Transfer ......... 18-22 Master Mode DMA Operation ..........18-24 Slave Mode DMA Operation ..........18-27 SPI Registers ................18-34 SPI Baud Rate (SPI_BAUD) Register ........18-35 SPI Control (SPI_CTL) Register ......... 18-36 SPI Flag (SPI_FLG) Register ..........
Page 35 Contents DMA-Based Transfer ............18-48 DMA Initialization Sequence .......... 18-49 SPI Initialization Sequence ..........18-50 Starting a Transfer ............18-51 Stopping a Transfer ............18-51 Unique Information for the ADSP-BF50x Processor ....18-54 SPORT CONTROLLER Specific Information for the ADSP-BF50x ........19-1 Overview ..................
Page 36 Contents Channel Selection Register ..........19-23 Multichannel DMA Data Packing ........19-24 Support for H.100 Standard Protocol ........19-25 2× Clock Recovery Control ..........19-25 Functional Description ............. 19-26 Clock and Frame Sync Frequencies ........19-26 Maximum Clock Rate Restrictions ........19-27 Word Length ..............
Page 37 Contents SPORT Registers ..............19-45 Register Writes and Effective Latency ........19-46 SPORT Transmit Configuration (SPORT_TCR1 and SPORT_TCR2) Registers ....19-47 SPORT Receive Configuration (SPORT_RCR1 and SPORT_RCR2) Registers ....19-52 Data Word Formats ............. 19-56 SPORT Transmit Data (SPORT_TX) Register ..... 19-57 SPORT Receive Data (SPORT_RX) Register .......
Page 38 Contents Unique Information for the ADSP-BF50x Processor ....19-76 PARALLEL PERIPHERAL INTERFACE Specific Information for the ADSP-BF50x ........20-1 Overview ..................20-2 Features ..................20-2 Interface Overview ..............20-3 Description of Operation ............20-4 Functional Description ............... 20-5 ITU-R 656 Modes ..............20-5 ITU-R 656 Background ............
Page 39 Contents Data Output (TX) Modes ..........20-17 No Frame Syncs ............20-17 1 or 2 External Frame Syncs ........20-18 1, 2, or 3 Internal Frame Syncs ........20-19 Frame Synchronization in GP Modes ....... 20-19 Modes With Internal Frame Syncs ....... 20-19 Modes With External Frame Syncs .......
Page 40 Contents Card Detection ..............21-11 RSI Power Saving Configuration ......... 21-14 RSI Commands and Responses ..........21-15 IDLE State ..............21-20 PEND State ..............21-20 SEND State ..............21-20 WAIT State ..............21-21 RECEIVE State .............. 21-21 CEATA_INT_WAIT State ..........21-22 CEATA_INT_DIS State ..........
Page 41 Contents Single Block Read Operation ..........21-39 Using Core ..............21-40 Using DMA ..............21-42 Multiple Block Write Operation ........... 21-43 Using Core ..............21-44 Using DMA ..............21-46 Multiple Block Read Operation ........... 21-48 Using Core ..............21-48 Using DMA ..............21-50 RSI Registers ................
Page 42 Contents RSI CE-ATA Control Register (RSI_CEATA_CONTROL) .. 21-74 RSI Data FIFO Register (RSI_FIFO) ........21-75 RSI Exception Status Register (RSI_ESTAT) ......21-75 RSI Exception Mask Register (RSI_EMASK) ....... 21-77 RSI Configuration Register (RSI_CONFIG) ....... 21-78 RSI Read Wait Enable Register (RSI_RD_WAIT_EN) ..21-80 RSI Peripheral ID Registers (RSI_PIDx) ......
Page 43 Contents ACM External Pin Timing ........... 22-20 Case 1—Chip Select Asserted During the High Phase of ACLK ................22-22 Case 2—Chip Select Asserted During the Low Phase of ACLK ................22-23 Case 3—Chip Select Asserted Right Before the Falling Edge of ACLK .............. 22-24 Case 4—Chip Select Asserted Right Before the Rising Edge of ACLK ..............
Page 44 Contents ANALOG/DIGITAL CONVERTER (ADC) ADC Architecture ............... 23-1 Maximum ADC Sampling Rate ........... 23-4 Interfacing the ADC With the ACM and the SPORT .... 23-4 Interfacing the ADC With the SPORT and With TMR Pins .. 23-6 SYSTEM RESET AND BOOTING Overview ..................
Page 45 Contents Boot Termination ..............24-20 Single Block Boot Streams ........... 24-21 Direct Code Execution ............ 24-22 Advanced Boot Techniques ............24-23 Initialization Code ............... 24-24 Quick Boot ................. 24-28 Indirect Booting ..............24-29 Callback Routines ..............24-30 Error Handler ..............24-32 CRC Checksum Calculation ..........
Page 46 Contents PPI Boot Mode ..............24-53 UART Slave Mode Boot ............24-55 Reset and Booting Registers ............24-59 Software Reset (SWRST) Register ........24-59 System Reset Configuration (SYSCR) Register ..... 24-61 Boot Code Revision Control (BK_REVISION) ....24-63 Boot Code Date Code (BK_DATECODE) ......24-64 Zero Word (BK_ZEROS) ............
Page 47 Contents BFROM_CRC32CALLBACK ..........24-81 BFROM_CRC32INITCODE ..........24-81 Programming Examples ............. 24-82 Example System Reset ............24-82 Example Exiting Reset to User Mode ........24-83 Example Exiting Reset to Supervisor Mode ......24-83 Example Power Management with Initcode ......24-84 Example XOR Checksum ............ 24-86 Example Direct Code Execution ..........
Page 48 Contents Oscilloscope Probes ............... 25-8 Recommended Reading ............25-9 Resetting the Processor ............. 25-10 Recommendations for Unused Pins ........... 25-10 Programmable Outputs ............. 25-11 Voltage Regulation Interface ............. 25-11 SYSTEM MMR ASSIGNMENTS Processor-Specific Memory Registers ..........A-2 Core Timer Registers ..............A-3 System Reset and Interrupt Control Registers ..................
Page 49 PWM Registers ................A-44 RSI Registers ................A-46 ACM Registers ................A-47 TEST FEATURES JTAG Standard ................B-1 Boundary-Scan Architecture ............B-2 Instruction Register ..............B-4 Public Instructions ..............B-6 EXTEST – Binary Code 00000 .......... B-6 SAMPLE/PRELOAD – Binary Code 10000 ....... B-6 BYPASS –...
Page 50 Contents ADSP-BF50x Blackfin Processor Hardware Reference...
Page 51: Preface
Intended Audience The primary audience for this manual is a programmer who is familiar with Analog Devices processors. The manual assumes the audience has a working knowledge of the appropriate processor architecture and instruc- tion set. Programmers who are unfamiliar with Analog Devices processors...
Page 52: Manual Contents
Manual Contents Manual Contents This manual contains: • Chapter 1, “Introduction” Provides a high level overview of the processor, including peripher- als, power management, and development tools. • Chapter 2, “Memory” Describes processor-specific memory topics, including L1memories and processor-specific memory MMRs. •...
Page 53 Preface • Chapter 9, “General-Purpose Ports” Describes the general-purpose I/O ports, including the structure of each port, multiplexing, configuring the pins, and generating interrupts. • Chapter 10, “General-Purpose Timers” Describes the eight general-purpose timers. • Chapter 11, “Core Timer” Describes the core timer. •...
Page 54 Manual Contents • Chapter 17, “CAN Module” Describes the CAN module, a low bit rate serial interface intended for use in applications where bit rates are typically up to 1Mbit/s. • Chapter 18, “SPI-Compatible Port Controller” Describes the Serial Peripheral Interface (SPI) port that provides an I/O interface to a variety of SPI compatible peripheral devices.
Page 55: What's New In This Manual
Preface • Chapter 24, “System Reset and Booting” Describes the booting methods, booting process and specific boot modes for the processor. • Chapter 25, “System Design” Describes how to use the processor as part of an overall system. It includes information about bus timing and latency numbers, sema- phores, and a discussion of the treatment of unused pins.
Page 56: Technical Support
Chapter 24, “System MOSI Reset and Booting” Technical Support You can reach Analog Devices processors and DSP technical support in the following ways: • Post your questions in the processors and DSP support community ® at EngineerZone http://ez.analog.com/community/dsp...
Page 57 • E-mail your questions about processors and processor applications processor.support@analog.com (Greater China support) processor.china@analog.com • In the USA only, call 1-800-ANALOGD (1-800-262-5643) • Contact your Analog Devices sales office or authorized distributor. Locate one at: www.analog.com/adi-sales • Send questions by mail to: Processors and DSP Technical Support Analog Devices, Inc.
Page 58: Supported Processors
Refer to the CCES or VisualDSP++ online help for a complete list of sup- ported processors. Product Information Product information can be obtained from the Analog Devices Web site and the CCES or VisualDSP++ online help. Analog Devices Web Site...
Page 59: Engineerzone
Preface EngineerZone EngineerZone is a technical support forum from Analog Devices, Inc. It allows you direct access to ADI technical support engineers. You can search FAQs and technical information to get quick answers to your embedded processing and DSP design questions.
Page 60: Notation Conventions
Notation Conventions Notation Conventions Text conventions in this manual are identified and described as follows. Example Description File > Close Titles in reference sections indicate the location of an item within the IDE environment’s menu system (for example, the Close command appears on the File menu).
Page 61: Register Diagram Conventions
Preface Register Diagram Conventions Register diagrams use the following conventions: • The descriptive name of the register appears at the top, followed by the short form of the name in parentheses. • If the register is read-only (RO), write-1-to-set (W1S), or write-1-to-clear (W1C), this information appears under the name.
Page 62 Register Diagram Conventions The following figure shows an example of these conventions. Timer Configuration Registers (TIMERx_CONFIG) 15 14 13 12 11 10 Reset = 0x0000 TMODE[1:0] (Timer Mode) ERR_TYP[1:0] (Error Type) - RO 00 - Reset state - unused. 00 - No error. 01 - PWM_OUT mode.
Page 63: Introduction
The ADSP-BF50x processors are members of the Blackfin processor fam- ily that offer significant high performance and low power features while retaining their ease-of-use benefits. The ADSP-BF504, ADSP-BF504F, and ADSP-BF506F processors have differing peripheral features. For details, see Table 1-1. Note that the ADSP-BF504 and ADSP-BF504F are pin-compatible.
Page 64 General Description of Processor Table 1-1. Processor Comparison Feature ADSP-BF504 ADSP-BF504F ADSP-BF506F Up/Down/Rotary Counters Timer/Counters with PWM 3-Phase PWM Units SPORTs SPIs UARTs Parallel Peripheral Interface Removable Storage Interface Internal 32M Bit Flash – ADC Control Module (ACM) Internal ADC –...
Page 65: Portable Low-Power Architecture
Introduction Portable Low-Power Architecture Blackfin processors provide world-class power management and perfor- mance. They are produced with a low-power and low-voltage design methodology and feature on-chip dynamic power management, which provides the ability to vary both the voltage and frequency of operation to significantly lower overall power consumption.
Page 66: Peripherals
Peripherals Peripherals The ADSP-BF50x processors contain a rich set of peripherals connected to the core via several high-bandwidth buses, providing flexibility in sys- tem configuration as well as excellent overall system performance. (See Figure 1-1.) Most of the peripherals are supported by a flexible DMA structure.
Page 67 The off-chip memory system, accessed through the external bus interface unit (EBIU), provides expansion with flash memory on the ADSP-BF504F and ADSP-BF506F processors. The memory DMA controller provides high bandwidth data movement capability. It can perform block transfers of code or data between the internal memory and the external memory spaces.
Page 68: Internal Memory
ROM. The EBIU on the processor interfaces with an internal flash memory on the ADSP-BF504F and ADSP-BF506F devices. The internal  chip flash memory is a 32M bit ( 16, multiple bank, burst) memory.
Page 69: I/O Memory Space
Introduction • Parameter blocks (top location) • Dual operations • Program erase in one bank while read in others • No delay between read and write operations • Block locking • All blocks locked at power-up • Any combination of blocks can be locked or locked down •...
Page 70: Dma Support
DMA Support DMA Support The processor has multiple, independent DMA channels that support automated data transfers with minimal overhead for the processor core. DMA transfers can occur between the processor’s internal memories and any of its DMA-capable peripherals. Additionally, DMA transfers can be accomplished between any of the DMA-capable peripherals and external devices connected to the external memory interface.
Page 71: General-Purpose I/O (Gpio)
Introduction In addition to the dedicated peripheral DMA channels, there are two memory DMA channels, which are provided for transfers between the var- ious memories of the processor system with minimal processor intervention. Memory DMA transfers can be controlled by a very flexible descriptor-based methodology or by a standard register-based autobuffer mechanism.
Page 72: Two-Wire Interface
Two-Wire Interface in order to toggle pin values, and one register is written in order to specify a pin value. Reading the GPIO status register allows soft- ware to interrogate the sense of the pins. • GPIO interrupt mask registers – The two GPIO interrupt mask registers allow each individual GPIO pin to function as an inter- rupt to the processor.
Page 73: Rsi Interface
Introduction The TWI externally moves 8-bit data while maintaining compliance with the I C bus protocol. The Philips I C Bus Specification version 2.1 covers many variants of I C. The TWI controller includes these features: • Simultaneous master and slave operation on multiple device systems •...
Page 74: General-Purpose (Gp) Counter
General-Purpose (GP) Counter The following list describes the main features of the RSI controller: • Support for a single MMC, SD memory, SDIO card or CE-ATA hard disk drive • Support for 1-bit and 4-bit SD modes • Support for 1-bit, 4-bit and 8-bit MMC modes •...
Page 75: 3-Phase Pwm Unit
Introduction 3-Phase PWM Unit The processors integrate two flexible and programmable 3-phase PWM waveform generators that can each be programmed to generate the required switching patterns to drive a 3-phase voltage source inverter for ac induction (ACIM) or permanent magnet synchronous (PMSM) motor control.
Page 76: Parallel Peripheral Interface
Parallel Peripheral Interface The six PWM output signals in each PWM controller consist of three high-side drive signals ( , and ) and three low-side PWM_AH PWM_BH PWM_CH drive signals ( , and ). The polarity of the generated PWM_AL PWM_BL PWM_CL PWM signal can be set with software, so that either active high or active...
Page 77 Introduction Three distinct ITU-R 656 modes are supported: • Active video only - The PPI does not read in any data between the End of Active Video (EAV) and Start of Active Video (SAV) pre- amble symbols, or any data present during the vertical blanking intervals.
Page 78: Sport Controllers
SPORT Controllers These modes support ADC/DAC connections, as well as video communi- cation with hardware signalling. Many of the modes support more than one level of frame synchronization. If desired, a programmable delay can be inserted between assertion of a frame sync and reception/transmission of data.
Page 79 Introduction • Framing Each transmit and receive port can run with or without frame sync signals for each data word. Frame sync signals can be generated internally or externally, active high or low, and with either of two pulse widths and early or late frame sync. •...
Page 80: Serial Peripheral Interface (Spi) Ports
Serial Peripheral Interface (SPI) Ports Serial Peripheral Interface (SPI) Ports The processor has two SPI-compatible ports that enable the processor to communicate with multiple SPI-compatible devices. Each SPI interface uses three pins for transferring data: two data pins and a clock pin. An SPI chip select input pin lets other SPI devices select the processor, and several SPI chip select output pins let the processor select other SPI devices.
Page 81: Uart Ports
Introduction The timers can generate interrupts to the processor core to provide peri- odic events for synchronization, either to the processor clock or to a count of external signals. In addition to the eight general-purpose programmable timers, a 9th timer is also provided.
Page 82 UART Ports Each UART port’s baud rate, serial data format, error code generation and status, and interrupts are programmable: • Supporting bit rates ranging from (f /1,048,576) to (f SCLK SCLK bits per second. • Supporting data formats from 7 to 12 bits per frame. •...
Page 83: Controller Area Network (Can) Interface
Introduction Controller Area Network (CAN) Interface The ADSP-BF50x processors provide a CAN controller that is a commu- nication controller implementing the Controller Area Network (CAN) V2.0B protocol. This protocol is an asynchronous communications proto- col used in both industrial and automotive control systems. CAN is well suited for control applications due to its capability to communicate reli- ably over a network since the protocol incorporates CRC checking, message error tracking, and fault node confinement.
Page 84: Acm Interface
The ADC control module (ACM) provides an interface that synchronizes the controls between the processor and analog-to-digital converter (ADC) modules like the internal ADC of the ADSP-BF506F. The analog-to-digi- tal conversions are initiated by the processor, based on external or internal events.
Page 85: Watchdog Timer
Introduction Watchdog Timer The processor includes a 32-bit timer that can be used to implement a software watchdog function. A software watchdog can improve system availability by forcing the processor to a known state through generation of a hardware reset, nonmaskable interrupt (NMI), or general-purpose interrupt, if the timer expires before being reset by software.
Page 86: Dynamic Power Management
Dynamic Power Management 64×) multiplication factor (bounded by specified minimum and maxi- frequencies). The default multiplier is 6×, but it can be modified by a software instruction sequence. On-the-fly frequency changes can be made by simply writing to the register. PLL_DIV All on-chip peripherals are clocked by the system clock ( ).
Page 87: Sleep Operating Mode-High Dynamic Power Savings
Introduction In the active mode, it is possible to disable the control input to the PLL by setting the PLL_OFF bit in the PLL control register. This register can be accessed with a user-callable routine in the on-chip ROM called bfrom_SysControl().
Page 88: Deep Sleep Operating Mode-Maximum Dynamic Power Savings
Dynamic Power Management Deep Sleep Operating Mode—Maximum Dynamic Power Savings The deep sleep mode maximizes dynamic power savings by disabling the clocks to the processor core (CCLK) and to all synchronous peripherals (SCLK). Asynchronous peripherals may still be running but cannot access internal resources or external memory.
Page 89: Instruction Set Description
Introduction enabled by the register. The signal indicates the occur- VR_CTL EXT_WAKE rence of a wakeup event. As long as V is applied, the register maintains its state dur- VR_CTL DDEXT ing hibernation. All other internal registers and memories, however, lose their content in the hibernate state.
Page 90: Development Tools
• Read and write core and peripheral registers • Plot memory Analog Devices DSP emulators use the IEEE 1149.1 JTAG test access port to monitor and control the target board processor during emulation. The emulator provides full speed emulation, allowing inspection and modification of memory, registers, and processor stacks.
Page 91 (boards and extenders). In addition to the software and hardware development tools available from Analog Devices, third parties provide a wide range of tools supporting the Blackfin processors. Third party software tools include DSP libraries, real-time operating systems, and block diagram design tools.
Page 92 Development Tools 1-30 ADSP-BF50x Blackfin Processor Hardware Reference...
Page 93: Memory
2 MEMORY This chapter discusses memory population specific to the ADSP-BF50x processors. Functional memory architecture is described in Blackfin Pro- cessor Programming Reference. Memory Architecture Figure 2-1 provides an overview of the ADSP-BF50x processor system memory map. For a detailed discussion of how to use them, see Blackfin Processor Programming Reference.
Page 94: L1 Instruction Sram
L1 Instruction SRAM 0xFFFF FFFF CORE MEMORY MAPPED REGISTERS 0xFFE0 0000 SYSTEM MEMORY MAPPED REGISTERS 0xFFC0 0000 RESERVED 0xFFB0 1000 INTERNAL SCRATCHPAD RAM (4K BYTES) 0xFFB0 0000 RESERVED 0xFFA1 4000 RESERVED 0xFFA0 8000 L1 INSTRUCTION SRAM/CACHE (16K BYTES) 0xFFA0 4000 L1 INSTRUCTION BANK A SRAM (16K BYTES) 0xFFA0 0000 RESERVED...
Page 95: L1 Data Sram
Memory Table 2-1 lists the memory start locations of the L1 instruction memory subbanks. Table 2-1. L1 Instruction Memory Subbanks Memory Start Location for Memory Subbank ADSP-BF50x Processors 0xFFA0 0000 0xFFA0 1000 0xFFA0 2000 0xFFA0 3000 0xFFA0 4000 0xFFA0 5000 0xFFA0 6000 0xFFA0 7000 L1 Data SRAM...
Page 96: L1 Data Cache
2-1) is accessed via the EBIU memory port. This 16-bit interface provides a glue-less connection to the internal flash memory (on ADSP-BF504F and ADSP-BF506F devices) and boot ROM. Internal flash memory ships from the factory in an erased state except for block 0 of the parameter bank.
Page 97: Processor-Specific Mmrs
Memory Processor-Specific MMRs The complete set of memory-related MMRs is described in the Blackfin Processor Programming Reference. Several MMRs have bit definitions spe- cific to the processors described in this manual. These registers are described in the following sections. DMEM_CONTROL Register The data memory control register ( ), shown in Figure...
Page 98: Dtest_Command Register
Processor-Specific MMRs DTEST_COMMAND Register When the data test command register ( ) is written to, the DTEST_COMMAND L1 cache data or tag arrays are accessed, and the data is transferred through the data test data registers ( ). This register is DTEST DATA[1:0] shown in Figure...
Page 99: Chip Bus Hierarchy
3 CHIP BUS HIERARCHY This chapter discusses on-chip buses, how data moves through the system, and other factors that determine the system organization. Following an overview and a list of key features is a block diagram of the chip bus hier- archy and a description of its operation.
Page 100: Interface Overview
• The peripheral set including GP timers and counters, ACM, TWI, RSI, UARTs, SPORTs, SPIs, PPI, watchdog timer, and PWM units. The ADSP-BF506F processor peripherals include an ADC and a flash memory, and the ADSP-BF504F processor peripherals include a flash memory (but does not include an ADC).
Page 101 Chip Bus Hierarchy CORE CLOCK (CCLK) DOMAIN L1 INSTR MEMORY VOLTAGE FLASH REGULATOR I/F L1 DATA MEMORY JTAG TEST AND EMULATION MEMORY BOOT PORT FLASH CTRL CTRL CONTROL PERIPHERAL WATCHDOG TIMER ACCESS BUS ACCESS BUS SYSTEM CLOCK (SCLK) DOMAIN Figure 3-1. Processor Bus Hierarchy ADSP-BF50x Blackfin Processor Hardware Reference...
Page 102: Core Bus Overview
Interface Overview The PAB, the DAB, the EAB, the DCB, the DEB, the EPB, and the EBIU run at system clock frequency (SCLK domain). This divider ratio is set using the SSEL parameter of the PLL divide (PLL_DIV) register and must be set so that these buses run as specified in the processor data sheet, and slower than or equal to the core clock frequency.
Page 103: Peripheral Access Bus (Pab)
Chip Bus Hierarchy SYSTEM CLOCK DSP ID JTAG AND POWER (8 BITS) MANAGEMENT DEBUG AND JTAG INTERFACE CORE EVENT CONTROLLER POWER AND RESET CLOCK VECTOR CONTROLLER PROCESSOR PERFORMANCE CORE TIMER MONITOR CORE MEMORY L1 INSTRUCTION L1 DATA MANAGEMENT UNIT DMA CORE BUS (DCB) Figure 3-2.
Page 104: Pab Arbitration
Interface Overview The core processor has byte addressability, but the programming model is restricted to only 32-bit (aligned) access to the system MMRs. Byte accesses to this region are not supported. PAB Arbitration The core is the only master on this bus. No arbitration is necessary. PAB Agents (Masters, Slaves) The processor core can master bus operations on the PAB.
Page 105: Pab Performance
Chip Bus Hierarchy • ACM • PWM • RSI • DMA controller PAB Performance For the PAB, the primary performance criteria is latency, not throughput. Transfer latencies for both read and write transfers on the PAB are two cycles. SCLK For example, the core can transfer up to 32 bits per access to the PAB slaves.
Page 106 Interface Overview The DCB has priority over the core processor on arbitration into L1 con- figured as data SRAM, whereas the core processor has priority over the DCB on arbitration into L1 instruction SRAM. For external memory (flash memory on ADSP-BF50xF processors), the core (by default) has priority over the DEB for accesses to the EPB.
Page 107: Dab Bus Agents (Masters)
Chip Bus Hierarchy Table 3-1. DAB, DCB, and DEB Arbitration Priority (Cont’d) Default Arbitration Priority DAB, DCB, DEB Master Mem DMA D1 has no peripheral mapping None Mem DMA S1 has no peripheral mapping None DAB Bus Agents (Masters) All peripherals capable of sourcing a DMA access are masters on this bus, as shown in Table 3-1.
Page 108: External Access Bus (Eab)
Interface Overview DMA access to L1 memory can only be stalled by an access already in progress from another DMA channel. Latencies caused by these stalls are in addition to any arbitration latencies.  The core processor and the DAB must arbitrate for access to exter- nal memory through the EBIU.
Page 109 Chip Bus Hierarchy Memory DMA transfers can result in repeated accesses to the same mem- ory location. Because the memory DMA controller has the potential of simultaneously accessing on-chip and off-chip memory, considerable throughput can be achieved. The throughput rate for an on-chip/off-chip memory access is limited by the slower of the two accesses.
Page 110 Interface Overview 3-12 ADSP-BF50x Blackfin Processor Hardware Reference...
Page 111: System Interrupts
Specific Information for the ADSP-BF50x For details regarding the number of system interrupts for the ADSP-BF50x product, refer to ADSP-BF504, ADSP-BF504F, ADSP-BF506F Embedded Processor Data Sheet. To determine how each of the system interrupts is multiplexed with other functional pins, refer to...
Page 112: Features
Description of Operation Features The Blackfin architecture provides a two-level interrupt processing scheme: • The core event controller (CEC) runs in the clock domain. It CCLK interacts closely with the program sequencer and manages the event vector table (EVT). The CEC processes not only core-related inter- rupts such as exceptions, core errors, and emulation events;...
Page 113 System Interrupts • Exceptions • Interrupts Note the word event describes all five types of activities. The CEC man- ages fifteen different events in all: emulation, reset, NMI, exception, and eleven interrupts. An interrupt is an event that changes the normal processor instruction flow and is asynchronous to program flow.
Page 114: System Peripheral Interrupts
Description of Operation Table 4-1. System and Core Event Mapping (Cont’d) Event Source Core Event Name System interrupts IVG7–IVG13 Software interrupt 1 IVG14 Software interrupt 2 (lowest priority) IVG15 System Peripheral Interrupts To service the rich set of peripherals, the SIC has multiple interrupt request inputs and outputs that go to the CEC.
Page 115 System Interrupts The core timer has a dedicated input to the CEC controller. Its interrupt is not routed through the SIC controller and always has higher priority than requests from all peripherals. register allows software to mask any peripheral interrupt SIC_IMASK source at the SIC level.
Page 116: Description Of Operation
Description of Operation  When an interrupt’s service routine is finished, the RTI instruction clears the appropriate bit in the register. However, the rele- IPEND vant bit is not cleared unless the service routine clears the SIC_ISR mechanism that generated the interrupt. Many systems need relatively few interrupt-enabled peripherals, allowing each peripheral to map to a unique core priority level.
Page 117: Programming Model
System Interrupts applications it may be desirable to disable this function for some peripher- als, such as for a SPORT transmit interrupt. The register can be SIC_IWR read from or written to at any time. To prevent spurious or lost interrupt activity, this register should be written to only when all peripheral inter- rupts are disabled.
Page 118: System Interrupt Initialization
Programming Model System Interrupt Initialization If the default peripheral-to-IVG assignments shown in Table 4-1 on page 4-3 Table 4-2 on page 4-11 are acceptable, then interrupt initial- ization involves only: • Initialization of the core event vector table (EVT) vector address entries •...
Page 119 System Interrupts masks off or enables events of different core priorities. If the IMASK event corresponding to interrupt A is not masked, the process IVGx proceeds to Step 7. 7. The event vector table (EVT) is accessed to look up the appropriate vector for interrupt A’s interrupt service routine (ISR).
Page 120: System Interrupt Controller Registers
System Interrupt Controller Registers RESET "INTERRUPT IVTMR A" IVHW PERIPHERAL CORE INTERRUPT CORE SYSTEM ASSIGN CORE EVENT REQUESTS INTERRUPT INTERRUPT SYSTEM VECTOR STATUS MASK MASK PRIORITY TABLE (ILAT) (IMASK) (SIC_IMASK) (SIC_IAR) (EVT[15:0]) SYSTEM SYSTEM CORE WAKEUP STATUS PENDING (SIC_IWR) (SIC_ISR) (IPEND) TO DYNAMIC POWER MANAGEMENT...
Page 121: System Interrupt Assignment (Sic_Iar) Register
System Interrupts System Interrupt Assignment (SIC_IAR) Register register maps each peripheral interrupt ID to a correspond- SIC_IAR ing IVG priority level. This is accomplished with 4-bit groupings that translate to IVG levels as shown in Table 4-2 Figure 4-2. In other words, Table 4-2 defines the value to write in a 4-bit field within...
Page 122: System Interrupt Mask (Sic_Imask) Register
System Interrupt Controller Registers Table 4-2. IVG Select Definitions (Cont’d) General-Purpose Interrupt Value in SIC_IAR IVG13 IVG14 IVG15 System Interrupt Mask (SIC_IMASK) Register register masks or enables peripheral interrupts at the sys- SIC_IMASK tem level. A “0” in a bit position masks off (disables) interrupts for that particular peripheral interrupt ID.
Page 123: Programming Examples
System Interrupts peripheral interrupt IDs are mapped to the register(s) for this par- SIC_IWR ticular processor. Programming Examples The following section provides an example for servicing interrupt requests. Clearing Interrupt Requests When the processor services a core event it automatically clears the requesting bit in the register and no further action is required by the ILAT...
Page 124 Programming Examples Listing 4-1 shows a representative example of how a GPIO interrupt request might be serviced. Listing 4-1. Servicing GPIO Interrupt Request #include <defBF527.h> /*ADSP-BF527 product is used as an example*/ .section program; _portg_a_isr: /* push used registers */ [--sp] = (r7:7, p5:5);...
Page 125: Unique Information For The Adsp-Bf50X Processor
System Interrupts instructions only, two instructions are recommended between the SSYNC clear command and the RTI instruction. However, one instruction SSYNC is typically sufficient if the clear command performs in the very beginning of the service routine, or the instruction is followed by another set SSYNC of instructions before the service routine returns.
Page 126 Unique Information for the ADSP-BF50x Processor  The memory-mapped , and registers are part of ILAT IMASK IPEND the CEC controller. IPEND IMASK ILAT PLL WAKEUP INTERRUPT DMA ERROR (GENERIC) PPI STATUS SPORT0 STATUS SPORT1 STATUS UART0 STATUS UART1 STATUS SPI0 STATUS SPI1 STATUS CAN STATUS...
Page 127 System Interrupts IPEND IMASK ILAT TIMER0 TIMER1 TIMER2 TIMER3 TIMER4 TIMER5 TIMER6 TIMER7 PORT G INTERRUPT A PORT G INTERRUPT B MDMA STREAM 0 MDMA STREAM 1 SOFTWARE WATCHDOG TIMER PORT H INTERRUPT A PORT H INTERRUPT B ACM STATUS INTERRUPT ACM INTERRUPT RESERVED RESERVED...
Page 128: System Peripheral Interrupts
Unique Information for the ADSP-BF50x Processor System Peripheral Interrupts Table 4-3 Table 4-4 show the peripheral interrupt events, the default mapping of each event, the peripheral interrupt ID used in the system interrupt assignment registers ( ), and the core interrupt ID. SIC_IAR Note that the system interrupt to core event mappings shown are the default values at reset and can be changed by software.
Page 129 System Interrupts Table 4-3. Peripheral Interrupt Events (Part 1) Peripheral Bit Position for SIC_IAR3-0 Interrupt Source Default ID Number SIC_ISR0, Mapping SIC_IMASK0, SIC_IWR0 Bit 31 SIC_IAR3[31:28] Reserved IVG11 Bit 30 SIC_IAR3[27:24] Port F Interrupt B IVG11 Bit 29 SIC_IAR3[23:20] Port F Interrupt A IVG11 Bit 28 SIC_IAR3[19:16]...
Page 130 Unique Information for the ADSP-BF50x Processor Table 4-3. Peripheral Interrupt Events (Part 1) (Cont’d) Peripheral Bit Position for SIC_IAR3-0 Interrupt Source Default ID Number SIC_ISR0, Mapping SIC_IMASK0, SIC_IWR0 Bit 7 SIC_IAR0[31:28] SPI0 Status IVG7 Bit 6 SIC_IAR0[27:24] UART1 Status IVG7 Bit 5 SIC_IAR0[23:20] UART0 Status...
Page 131 System Interrupts Table 4-4. Peripheral Interrupt Events (Part 2) (Cont’d) Peripheral Bit Position for SIC_IAR7–4 Interrupt Source Default ID Number SIC_ISR1, Mapping SIC_IMASK1, SIC_IWR1 Bit 20 SIC_IAR6[19:16] PWM0 Sync Interrupt IVG10 Bit 19 SIC_IAR6[15:12] PWM0 Trip Interrupt IVG10 Bit 18 SIC_IAR6[11:8] Reserved IVG7...
Page 132 Unique Information for the ADSP-BF50x Processor 4-22 ADSP-BF50x Blackfin Processor Hardware Reference...
Page 133: External Bus Interface Unit
UNIT The external bus interface unit (EBIU) on the ADSP-BF50x Blackfin pro- cessors provides glue-less interface to the internal parallel flash memory, which is available on ADSP-BF504F and ADSP-BF506F Blackfin proces- sors, and to the processor boot ROM.  On the ADSP-BF50x Blackfin processors, the parallel synchronous internal flash memory is internal to the product package, but this memory is external to the processor.
Page 134 0xEEFF FFFF RESERVED 0x2040 0000 SYNCHRONOUS FLASH MEMORY (4 MBYTES)* 0x2000 0000 RESERVED 0x0000 0000 * THE SYNCHRONOUS FLASH MEMORY IS AVAILABLE ONLY ON THE ADSP-BF504F AND ADSP-BF506F PROCESSORS. Figure 5-1. ADSP-BF50x External Memory Map ADSP-BF50x Blackfin Processor Hardware Reference...
Page 135: Block Diagram
0x0000 0000 up to address 0x2000 0000 is reserved. On ADSP-BF50x Blackfin processors that feature internal parallel flash memories (ADSP-BF504F and ADSP-BF506F), the region from 0x2000 0000 to 0x2040 0000 is dedicated to supporting the 4M Bytes internal parallel synchronous flash memory.
Page 136: Internal Memory Interfaces
EBIU Overview Note that—because the EBIU memory-interface signals do not come out to package pins—no external memory devices can be supported by the EBIU in ADSP-BF50x Blackfin processors. Internal Memory Interfaces The EBIU functions as a slave on three buses internal to the processor: •...
Page 137: Error Detection
External Bus Interface Unit • Mode control register ( EBIU_MODE • Parameter control register ( EBIU_FCTL Each of these registers is described in detail in the later sections of this chapter. Error Detection The EBIU responds to any bus operation which addresses the range of 0x0000 0000 –...
Page 138: Features
AMC Description of Operation Features The EBIU AMC features include: • 16-bit I/O width • 3.3 V I/O supply • Supports instruction fetch • Allows booting Asynchronous Memory Interface The asynchronous memory interface allows a glue-less interface to internal flash memory. Asynchronous Memory Address Decode The address range allocated per bank is fixed at 4M bytes.
Page 139: Amc Programming Model
External Bus Interface Unit One case where contention can occur is a read followed by a write to the same memory space. In this case, the data bus drivers can potentially con- tend with those of the memory device addressed by the read. To avoid contention, program the turnaround time (bank transition time) appropriately in the asynchronous memory bank control registers.
Page 140 AMC Programming Model • Asynchronous memory bank enable (AMBEN). If a bus operation accesses a disabled asynchronous memory bank, the EBIU responds by acknowledging the transfer and asserting the error signal on the requesting bus. The error signal propagates back to the requesting bus master.
Page 141: Ebiu Registers
External Bus Interface Unit The timing characteristics of the AMC can be programmed using these four parameters: • Setup: the time between the beginning of a memory cycle ( low) and the read-enable assertion ( low) or write-enable assertion low). •...
Page 142: Ebiu_Amgctl Register
EBIU Registers EBIU_AMGCTL Register Figure 5-3 shows the asynchronous memory global control register EBIU_AMGCTL Asynchronous Memory Global Control Register (EBIU_AMGCTL) 15 14 13 12 11 10 0xFFC0 0A00 Reset = 0x00F3 AMCKEN CDPRIO 0 - Core has priority over DMA 0 - Disable CLKOUT for for external accesses asynchronous memory...
Page 143: Ebiu_Ambctl Register
External Bus Interface Unit EBIU_AMBCTL Register Figure 5-4 shows the asynchronous memory bank control register EBIU_AMBCTL Asynchronous Memory Bank Control Register (EBIU_AMBCTL) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset = 0x0000 FFC2 0xFFC0 0A04 15 14 13 12 11 10 B0WAT[3:0]...
Page 144: Ebiu_Modectl Register
EBIU Registers EBIU_MODECTL Register Figure 5-5 shows the asynchronous memory mode control register EBIU_MODECTL Asynchronous Memory Mode Control Register (EBIU_MODECTL) 15 14 13 12 11 10 0xFFC0 0A20 Reset = 0x0001 B0MODE[1:0] Flash memory access mode 00 - Reserved 01 - Asynchronous flash mode 10 - Reserved 11 - Synchronous burst flash mode Figure 5-5.
Page 145: Internal Flash Memory
6 INTERNAL FLASH MEMORY ADSP-BF50xF Blackfin processors interface to a 32M bit (2M x 16) device. The internal flash memory has an array of 71 blocks, and is divided into 4M bit banks. There are 7 banks each containing 8 main blocks of 32K words, and one parameter bank containing 8 parameter blocks of 4K words and 7 main blocks of 32K words.
Page 146 Overview Table 6-1. EBIU/Internal Flash Memory Internal Pin Connections EBIU Pins Stacked Flash Pins Comment Address pins A21-A1 A20-A0 Data D15-D0 D15-D0 Chip enable AMS0 Output enable Latch enable (address valid) Burst clock NOR_CLK Wait ARDY WAIT Write enable Write protect (tied low) —...
Page 147 Internal Flash Memory A0-A20 DQ0-DQ15 WAIT INTERNAL FLASH MEMORY Figure 6-1. Internal Flash Memory Connections Table 6-2. Internal Flash Memory Signal Names Signal Name Function Direction Address inputs Inputs A0-A20 Data input/outputs, command inputs D0-D15 Chip Enable Input Output Enable Input Write Enable Input...
Page 148 Overview Table 6-2. Internal Flash Memory Signal Names (Cont’d) Signal Name Function Direction Supply voltage for input/output buffers Input V DDFLASH Global program/erase protect Input V PP Ground V SS The internal flash memory features an asymmetrical block architecture. The internal flash memory has an array of 71 blocks, and is divided into 4M bit banks.
Page 149 Internal Flash Memory Each block can be erased separately. Erase can be suspended to perform program in any other block, and then resumed. Program can be suspended to read data in any other block and then resumed. Each block can be pro- grammed and erased over 100,000 cycles.
Page 150: Command Interface To Internal Flash Memory
Command Interface to Internal Flash Memory The device includes a protection register to increase the protection of a system’s design. The protection register is divided into two segments: a 64-bit segment containing a unique device number and a 128-bit segment one-time-programmable (OTP) by the user.
Page 151: Command Interface - Standard Commands
Internal Flash Memory Table 6-4. Command Codes (Cont’d) Hex Code Command 0x40 Program Setup 0x50 Clear Status Register 0x60 Block Lock Setup, Block Unlock Setup, Block Lock Down Setup and Set Configuration Register Setup 0x70 Read Status Register 0x90 Read Electronic Signature 0x98 Read CFI Query 0xB0...
Page 152: Read Status Register Command
Command Interface to Internal Flash Memory Read Status Register Command The status register indicates when a program or erase operation is com- plete and the success or failure of operation itself. Issue a read status register command to read the status register content. The read status regis- ter command can be issued at any time, even during program or erase operations.
Page 153: Read Cfi Query Command
Internal Flash Memory Read CFI Query Command The read CFI query command reads data from the common flash interface (CFI). The read CFI query command consists of one bus write cycle to an address within one of the banks. Once the command is issued subsequent bus read operations in the same bank read from the common flash interface.
Page 154: Block Erase Command
“Dual Operations and Multiple Bank Architecture” on page 6-36 for detailed information about simultaneous operations allowed in banks not being erased. Typical erase times are given in the ADSP-BF504, ADSP-BF504F, ADSP-BF506F Embedded Processor Data Sheet. Figure 6-7 on page 6-60 Listing 6-3 on page 6-61 for a suggested flowchart and pseudo code for using the block erase command.
Page 155: Program Command
Typical program times are given in the ADSP-BF504, ADSP-BF504F, ADSP-BF506F Embedded Processor Data Sheet. Programming aborts if reset is asserted ( driven low). As data integrity cannot be guaranteed when the program operation is aborted, the internal flash memory device location must be reprogrammed.
Page 156: Program/Erase Resume Command
Command Interface to Internal Flash Memory One bus write cycle is required to issue the program/erase suspend com- mand. Once the program/erase controller has paused bits and/or of the status register are set to ‘1’. The command can be addressed to any bank.
Page 157: Protection Register Program Command
Internal Flash Memory The program/erase resume command does not change the read mode of the banks. If the suspended bank is in read status register, read electronic signature or read CFI query mode the bank remains in that mode and outputs the corresponding data.
Page 158: The Set Configuration Register Command
Command Interface to Internal Flash Memory protection of the protection register is not reversible. The protection regis- ter program cannot be suspended. Dual operations between the parameter bank and the protection register internal flash memory space are not allowed (see Table 6-14 on page 6-38).
Page 159: Block Unlock Command
Internal Flash Memory The lock status can be monitored for each block using the read electronic signature command. Table 16 shows the lock status after issuing a block lock command. The block lock bits are volatile; once set they remain set until a hardware reset or power-down/power-up.
Page 160 Command Interface to Internal Flash Memory Two bus write cycles are required to issue the block lock-down command: • The first bus cycle sets up the block lock command. • The second bus write cycle latches the block address. The lock status can be monitored for each block using the read electronic signature command.
Page 161 Internal Flash Memory Table 6-5. Standard Commands (Cont’d) Commands Cycles Bus Operations 1st Cycle 2nd Cycle Data Data Block Lock Write BKA or 0x60 Write 0x01 Block Unlock Write BKA or 0x60 Write 0xD0 Block Lock-Down Write BKA or 0x60 Write 0x2F 1 X = ‘don't care’, WA = Word Address in targeted bank, RD = Read Data, SRD = Status Register...
Page 162: Status Register
Command Interface to Internal Flash Memory Table 6-6. Electronic Signature Codes (Cont’d) Code Address (h) Data (h) Protection Register Factory default Bank address + 80 0002 Lock OTP area perma- 0000 nently locked Protection Register Bank address + 81 Unique device number Bank address + 84 Bank address + 85 OTP Area...
Page 163: Program/Erase Controller Status Bit (Sr7)
Internal Flash Memory deasserted. The status register can only be read using single asynchronous or single synchronous reads. Bus read operations from any address within the bank always read the status register during program and erase opera- tions, as long as no read array command has been issued. The various bits convey information about the status and any errors of the operation.
Page 164: Erase Suspend Status Bit (Sr6)
Command Interface to Internal Flash Memory After the program/erase controller completes its operation the erase status, program status, status and block lock status bits should be tested for errors. Erase Suspend Status Bit (SR6) The erase suspend status bit indicates that an erase operation has been sus- pended or is going to be suspended in the addressed block.
Page 165: Program Status Bit (Sr4)
Internal Flash Memory Program Status Bit (SR4) The program status bit identifies a program failure. When the program status bit is high (set to ‘1’), the program/erase con- troller has applied the maximum number of pulses to the byte and still failed to verify that it has programmed correctly.
Page 166: Program Suspend Status Bit (Sr2)
Command Interface to Internal Flash Memory Program Suspend Status Bit (SR2) The program suspend status bit indicates that a program operation has been suspended in the addressed block. When the program suspend status bit is high (set to ‘1’), a program/erase suspend command has been issued and the internal flash memory is waiting for a program/erase resume com- mand.
Page 167 Internal Flash Memory When both the program/erase controller status bit and the bank write sta- tus bit are low (set to ‘0’), the addressed bank is executing a program or erase operation. When the program/erase controller status bit is low (set to ‘0’) and the bank write status bit is high (set to ‘1’), a program or erase operation is being executed in a bank other than the one being addressed.
Page 168: Configuration Register
Command Interface to Internal Flash Memory Table 6-7. Status Register Bits (Cont’d) Name Type Logic Definition level Bank write status Status SR7 = ‘1’ Not allowed SR7 = ‘0’ Program or erase operation in a bank other than the addressed bank SR7 = ‘1’...
Page 169: Latency Bits (Cr13-Cr11)
Internal Flash Memory are asynchronous; when the read select bit is set to ‘0’, read operations are synchronous. Synchronous burst read is supported in both parameter and main blocks and can be performed across banks. On reset or power-up the read select bit is set to ‘1’ for asynchronous access.
Page 170: Data Output Configuration Bit (Cr9)
Command Interface to Internal Flash Memory Data Output Configuration Bit (CR9) The data output configuration bit determines whether the output remains valid for one or two clock cycles. When the data output configuration bit is ‘0’ the output data is valid for one clock cycle. When the data output configuration bit is ‘1’...
Page 171: Wait Configuration Bit (Cr8)
Internal Flash Memory Wait Configuration Bit (CR8) In burst mode, the wait bit controls the timing of the wait output pin, . When is asserted, data is not valid and when is deasserted, WAIT WAIT WAIT data is valid. When the wait bit is ‘0’ the wait output pin is asserted during the wait state.
Page 172 Command Interface to Internal Flash Memory They can be set for 4 words, 8 words, 16 words or continuous burst, where all the words are read sequentially. In continuous burst mode the burst sequence can cross bank boundaries. In continuous burst mode or in 4, 8, 16 words no-wrap, depending on the starting address, the device asserts the output to indicate that a delay WAIT...
Page 173 Internal Flash Memory Table 6-9. Configuration Register Bits (Cont’d) Description Value Description Wait Polarity WAIT is active low CR10 WAIT is active high (default) Data Output Configura- Data held for one clock cycle tion Data held for two clock cycles (default) Wait Configuration WAIT is active during wait state WAIT is active one data cycle before wait...
Page 174 Command Interface to Internal Flash Memory A20-A0 VALID ADDRESS D15-D0 VALID DATA VALID DATA NOT VALID VALID DATA WAIT CR8 = 0 CR10 = 0 WAIT CR8 = 1 CR10 = 0 WAIT CR8 = 0 CR10 = 1 WAIT CR8 = 1 CR10 = 1 Figure 6-4.
Page 175 Internal Flash Memory Table 6-10. Burst Type Definition (Wrap Mode) (Cont’d) Start 4 Words 8 Words 16 Words Continuous Burst Sequential Interleaved Sequential Interleaved Sequential Interleaved 3-0-1-2 3-2-1-0 3-4-5-6- 3-2-1-0-7- 3-4-5-6-7- 3-2-1-0-7- 3-4-5-6-7...15- 7-0-1-2 6-5-4 8-9-10-11- 6-5-4-11- WAIT-WAIT- 12-13-14- 10-9-8-15- WAIT-16-17- 15-0-1-2 14-13-12...
Page 176 Command Interface to Internal Flash Memory Table 6-11. Burst Type Definition (No-Wrap Mode) Start 4 Words 8 Words 16 Words Continuous Burst Sequential Sequential Sequential 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7-8-9-10- Same as for Wrap 11-12-13-14-15 (Wrap/No Wrap has no effect on 1-2-3-4 1-2-3-4-5-6-7-8 1-2-3-4-5-6-7-8-9-10- Continuous Burst)
Page 177: Read Modes
Internal Flash Memory Read Modes Read operations can be performed in two different ways depending on the settings in the configuration register. If the clock signal is ‘don’t care’ for the data output, the read operation is asynchronous. If the data output is synchronized with clock, the read operation is synchronous.
Page 178 Command Interface to Internal Flash Memory Synchronous burst read mode can only be used to read the internal flash memory array. For other read operations, such as read status register, read CFI, and read electronic signature, single synchronous read or asynchro- nous random access read must be used.
Page 179: Synchronous Burst Read Suspend
Internal Flash Memory continuous burst read mode a wait state occurs when crossing the first 16- word boundary. If the burst starting address is aligned to a 4-word page, the wait state does not occur. signal can be configured to be active low or active high by set- WAIT ting in the configuration register.
Page 180: Single Synchronous Read Mode
Command Interface to Internal Flash Memory Single Synchronous Read Mode Single synchronous read operations are similar to synchronous burst read operations except that only the first data output after the X latency is valid. Synchronous single reads are used to read the electronic signature, status register, CFI, block protection status, configuration register status or protection register status.
Page 181 Internal Flash Memory Table 6-12 Table 6-13 show the dual operations possible in other banks and in the same bank. For a complete list of possible commands refer to “Command Interface State Tables” on page 6-68. Table 6-12. Dual Operations Allowed in Other Banks Status of Bank Commands Allowed in Another Bank Read...
Page 182: Block Locking
Command Interface to Internal Flash Memory Table 6-14. Dual Operation Limitations Current Status Commands Allowed Read CFI/OTP/ Read Read Main Blocks Electronic Parameter Located in Not located in Signature Blocks Parameter Bank Parameter Bank Programming/erasing parameter blocks Programming/ Located in erasing main parameter bank blocks...
Page 183: Reading A Block's Lock Status
Internal Flash Memory Reading a Block’s Lock Status The lock status of every block can be read in the read electronic signature mode of the device. To enter this mode write 0x90 to the device. Subse- quent reads at the address specified in Table 6-6 on page 6-17 output the protection status of that block.
Page 184: Lock-Down State
Command Interface to Internal Flash Memory Lock-Down State Blocks that are locked-down (state (0,1,x)) are protected from program and erase operations (as for locked blocks) but their protection status can- not be changed using software commands alone. A locked or unlocked block can be locked-down by issuing the lock-down command.
Page 185 Internal Flash Memory Refer to “Command Interface State Tables” on page 6-68 for detailed information on which commands are valid during erase suspend. Table 6-15. Lock Status Current Protection Status Next Protection Status (D1, D0) (D1, D0) Current State Program/Erase After Block Lock After Block After Block...
Page 186: Block Address Table
Block Address Table Block Address Table Table 6-16 lists the top boot block addresses Table 6-16. Top Boot Block Addresses Size Address Range Bank (K word) Parameter Bank 0x203FE000 - 0x203FFFFE 0x203FC000 - 0x203FDFFE 0x203FA000 - 0x203FBFFE 0x203F8000 - 0x203F9FFE 0x203F6000 - 0x203F7FFE 0x203F4000 - 0x203F5FFE 0x203F2000 - 0x203F3FFE...
Page 187 Internal Flash Memory Table 6-16. Top Boot Block Addresses (Cont’d) Size Address Range Bank (K word) Bank 1 0x20370000 - 0x2037FFFE 0x20360000 - 0x2036FFFE 0x20350000 - 0x2035FFFE 0x20340000 - 0x2034FFFE 0x20330000 - 0x2033FFFE 0x20320000 - 0x2032FFFE 0x20310000 - 0x2031FFFE 0x20300000 - 0x2030FFFE Bank 2 0x202F0000 - 0x202FFFFE 0x202E0000 - 0x202EFFFE...
Page 188 Block Address Table Table 6-16. Top Boot Block Addresses (Cont’d) Size Address Range Bank (K word) Bank 4 0x201F0000 - 0x201FFFFE 0x201E0000 - 0x201EFFFE 0x201D0000 - 0x201DFFFE 0x201C0000 - 0x201CFFFE 0x201B0000 - 0x201BFFFE 0x201A0000 - 0x201AFFFE 0x20190000 - 0x2019FFFE 0x20180000 - 0x2018FFFE Bank 5 0x20170000 - 0x2017FFFE 0x20160000 - 0x2016FFFE...
Page 189: Common Flash Interface
Internal Flash Memory Table 6-16. Top Boot Block Addresses (Cont’d) Size Address Range Bank (K word) Bank 7 0x20070000 - 0x2007FFFE 0x20060000 - 0x2006FFFE 0x20050000 - 0x2005FFFE 0x20040000 - 0x2004FFFE 0x20030000 - 0x2003FFFE 0x20020000 - 0x2002FFFE 0x20010000 - 0x2001FFFE 0x20000000 - 0x2000FFFE 1 There are two bank regions: bank region 1 contains all the banks that are made up of main blocks only;...
Page 190 Common Flash Interface accessed only in read mode by the final user. It is impossible to change the security number after it has been written by the factory. Issue a read array command to return to read mode. Table 6-17. Query Structure Overview Offset Sub-Section Name Description...
Page 191 Internal Flash Memory Table 6-18. CFI Query Identification String (Cont’d) Offset Sub-Section Name Description Value 0x13 0x14 0x0003 Primary algorithm command set and 0x0000 control interface ID code 16 bit ID code defining a specific algorithm 0x15 0x16 offset = P = 0x0039 Address for primary algorithm extended p = 0x39 0x0000...
Page 192 Common Flash Interface Table 6-19. CFI Query System Interface Information (Cont’d) Offset Data Description Value 0x23 0x0003 128 µs Maximum time-out for word program = 2 times typical 0x24 0x0000 Maximum time-out for multi-byte programming = 2 times typical 0x25 0x0002 times typical 4 s Maximum time-out per individual block erase = 2...
Page 193 Internal Flash Memory Table 6-21. Primary Algorithm-Specific Extended Query Table Offset Data Description Value 0x(P) = 0x39 0x0050 Primary algorithm extended query table unique ASCII "P" 0x0052 string “PRI” "R" 0x0049 "I" 0x(P+3) = 0x3C 0x0031 Major version number, ASCII "1"...
Page 194 Common Flash Interface Table 6-21. Primary Algorithm-Specific Extended Query Table (Cont’d) Offset Data Description Value 0x(P+A) = 0x43 0x0003 Block protect status Defines which bits in the block status register section of the query are implemented. 0x(P+B) = 0x44 0x0000 Bit 0 block protect status register lock/unlock bit active (1 = Yes, 0 = No Bit 1 block lock status register lock-down bit active...
Page 195 Internal Flash Memory Table 6-23. Burst Read Information Offset Data Description Value 0x(P+13) = 0x4C 0x0003 Page-mode read capability 8 bytes Bits 0-7 ‘n’ such that 2 HEX value represents the number of read-page bytes. See offset 0x28 for device word width to determine page-mode data output width.
Page 196 Common Flash Interface Table 6-25. Bank and Erase Block Region 1 Information Internal Flash Region 1 Description Offset Data 0x(P+1A) = 0x53 0x07 Number of identical banks within bank region 1 0x(P+1B) = 0x54 0x00 0x(P+1C) = 0x55 0x11 Number of program or erase operations allowed in bank region 1: Bits 0-3: number of simultaneous program operations Bits 4-7: number of simultaneous erase operations 0x(P+1D) = 0x56...
Page 197 Internal Flash Memory Table 6-25. Bank and Erase Block Region 1 Information (Cont’d) Internal Flash Region 1 Description Offset Data 0x(P+26) = 0x5F 0x01 Bank region 1 (erase block type 1): bits per cell, internal ECC Bits 0-3: bits per cell in erase region Bit 4: reserved for “internal ECC used”...
Page 198 Common Flash Interface Table 6-26. Bank and Erase Block Region 2 Information (Cont’d) Internal Flash Region 2 Description Offset Data 0x(P+2D) = 0x66 0x02 Types of erase block regions in bank region 2 n = number of erase block regions with contiguous same-size erase blocks Symmetrically blocked banks have one blocking region.
Page 199 Internal Flash Memory Table 6-26. Bank and Erase Block Region 2 Information (Cont’d) Internal Flash Region 2 Description Offset Data 0x(P+3C) = 0x75 0x01 Bank region 2 (erase block type 2): bits per cell, internal ECC Bits 0-3: bits per cell in erase region Bit 4: reserved for “internal ECC used”...
Page 200: Flowcharts And Pseudo Codes
Flowcharts and Pseudo Codes Flowcharts and Pseudo Codes START WRITE 0x40 or 0x10 WRITE ADDRESS AND DATA READ STATUS REGISTER SR7 = 1 SR3 = 0 INVALID ERROR SR4 = 0 PROGRAM ERROR PROGRAM TO PROTECTED SR1 = 0 BLOCK ERROR Figure 6-5.
Page 201 Internal Flash Memory Listing 6-1. Program Pseudo Code program_command (addressToProgram, dataToProgram) {: " writeToFlash (addressToProgram, 0x40); /*writeToFlash (addressToProgram, 0x10);*/ /*see note (3)*/ " writeToFlash (addressToProgram, dataToProgram) ; /*Memory enters read status state after the Program Command*/ do { status_register=readFlash (addressToProgram); "see note (3)";...
Page 202 Flowcharts and Pseudo Codes START WRITE 0xB0 WRITE 0x70 READ STATUS REGISTER SR7 = 1 SR2 = 1 PROGRAM COMPLETE WRITE 0xFF WRITE 0xFF READ DATA READ DATA FROM ANOTHER ADDRESS WRITE 0xD0 WRITE 0x70 PROGRAM CONTINUES WITH BANK IN READ STATUS REGISTER MODE Figure 6-6.
Page 203 Internal Flash Memory Listing 6-2. Program Suspend and Resume Pseudo Code program_suspend_command ( ) { writeToFlash (any_address, 0xB0) ; writeToFlash (bank_address, 0x70) ; /* read status register to check if program has already completed */ do { status_register=readFlash (bank_address) ; /* E or G must be toggled*/ } while (status_register.SR7== 0) ;...
Page 204 Flowcharts and Pseudo Codes START WRITE 0x20 WRITE BLOCK ADDRESS AND 0xD0 READ STATUS REGISTER SR7 = 1 SR3 = 0 INVALID ERROR COMMAND SEQUENCE SR4, SR5 = 1 ERROR SR5 = 0 ERASE ERROR ERASE TO PROTECTED SR1 = 0 BLOCK ERROR Figure 6-7.
Page 205 Internal Flash Memory Listing 6-3. Block Erase Pseudo Code erase_command ( blockToErase ) { writeToFlash (blockToErase, 0x20) ; /*see note (2) */ writeToFlash (blockToErase, 0xD0) ; /* only A12-A20 are significant */ /* Memory enters read status state after the Erase Command */ do { status_register=readFlash (blockToErase) ;...
Page 206 Flowcharts and Pseudo Codes START WRITE 0xB0 WRITE 0x70 READ STATUS REGISTER SR7 = 1 SR6 = 1 ERASE COMPLETE WRITE 0xFF WRITE 0xFF READ DATA Read data from another block, Program, Set Configuration Register or Block Lock/Unlock/Lock-Down WRITE 0xD0 WRITE 0x70 ERASE CONTINUES WITH BANK IN READ STATUS...
Page 207 Internal Flash Memory Listing 6-4. Erase Suspend and Resume Pseudo Code erase_suspend_command ( ) { writeToFlash (bank_address, 0xB0) ; writeToFlash (bank_address, 0x70) ; /* read status register to check if erase has already completed */ do { status_register=readFlash (bank_address) ; /* E or G must be toggled*/ } while (status_register.SR7== 0) ;...
Page 208 Flowcharts and Pseudo Codes /*read status register to check if erase has completed */ START WRITE 0x60 WRITE 0x01, 0xD0, or 0x2F WRITE 0x90 READ BLOCK LOCK STATES LOCKING CHANGE CONFIRMED? WRITE 0xFF Figure 6-9. Locking Operations Flowchart 1 Any address within the bank can equally be used. Listing 6-5.
Page 209 Internal Flash Memory if (lock_operation==LOCK) /*to protect the block*/ writeToFlash (address, 0x01) ; else if (lock_operation==UNLOCK) /*to unprotect the block*/ writeToFlash (address, 0xD0) ; else if (lock_operation==LOCK-DOWN) /*to lock the block*/ writeToFlash (address, 0x2F) ; writeToFlash (address, 0x90) ; /*see note (1) */ if (readFlash (address) ! = locking_state_expected) error_handler () ;...
Page 210 Flowcharts and Pseudo Codes START WRITE 0xC0 WRITE ADDRESS AND DATA READ STATUS REGISTER SR7 = 1 SR3 = 0 INVALID ERROR SR4 = 0 PROGRAM ERROR PROGRAM TO PROTECTED SR1 = 0 BLOCK ERROR Figure 6-10. Protection Register Program Flowchart 1 Status check of SR1 (protected block), SR3 (V invalid) and SR4 (program error) can be made after each program operation or after a sequence.
Page 211 Internal Flash Memory Listing 6-6. Protection Register Program Pseudo Code protection_register_program_command (addressToProgram, dataToProgram) {: writeToFlash (addressToProgram, 0xC0) ; /*see note (3) */ writeToFlash (addressToProgram, dataToProgram) ; /*Memory enters read status state after the Program Command*/ do { status_register=readFlash (addressToProgram) ; /* see note (3) */ /* E or G must be toggled*/ } while (status_register.SR7== 0) ;...
Page 212: Command Interface State Tables
Command Interface State Tables Command Interface State Tables Table 6-27. Command Interface States – Modify Table, Next State Command Input Current CI State Ready Ready Program Erase Ready Setup Setup Lock/CR Setup Ready (Lock Error) Ready Ready (Lock Error) Setup OTP Busy Busy IS in OTP Busy...
Page 213 Internal Flash Memory Table 6-27. Command Interface States – Modify Table, Next State (Cont’d) Command Input Current CI State Setup Ready (Error) Erase Busy Ready (error) Busy Erase IS in Erase Busy Erase Busy Erase Busy Busy IS in Erase Erase Busy Erase Busy...
Page 214 Command Interface State Tables Table 6-27. Command Interface States – Modify Table, Next State (Cont’d) Command Input Current CI State Setup Program Busy in Erase Suspend Prog. IS in Program Prog. Busy PS in Busy Busy in Busy in Erase in ES Program Busy in Erase Suspend Suspend...
Page 215 Internal Flash Memory Table 6-28. Command Interface States – Modify Table, Next Output Command Input Current CI State Program Setup Erase Setup OTP Setup Program Setup in Status Register Erase Suspend Lock/CR Setup Lock/CR Setup in Erase Suspend ADSP-BF50x Blackfin Processor Hardware Reference 6-71...
Page 216 Command Interface State Tables Table 6-28. Command Interface States – Modify Table, Next Output (Cont’d) Command Input Current CI State OTP Busy Status Register Ready Program Busy Erase Busy Program Electronic Array Status Output Status Output /Erase Signature / Register Unchanged Register Unchanged...
Page 217 Internal Flash Memory 5 If the P/EC is active, both cycles are ignored. 6 The clear status register command clears the status register error bits except when the P/EC is busy or suspended. Table 6-29. Command Interface States – Lock Table, Next State Command Input Lock/CR Block...
Page 218 Command Interface State Tables Table 6-29. Command Interface States – Lock Table, Next State (Cont’d) Command Input Lock/CR Block Block Set CR P/E. C. Illegal Command Current CI State Lock Lock- Confirm Operation Setup Setup Confirm Down (0x03) Completed (0x60) (0xC0) (0x01) Confirm...
Page 219 Internal Flash Memory Table 6-30. Command Interface States – Lock Table, Next Output Current CI Command Input State Lock/CR Block Block Set CR Illegal . C. Lock Lock- Confirm Operation Setup Setup Command Confirm Down (0x03) Completed (0x60) (0xC0) (0x01) Confirm (0x2F) Program Setup...
Page 220 Command Interface State Tables Table 6-30. Command Interface States – Lock Table, Next Output (Cont’d) Current CI Command Input State Lock/CR Block Block Set CR Illegal . C. Lock Lock- Confirm Operation Setup Setup Command Confirm Down (0x03) Completed (0x60) (0xC0) (0x01) Confirm...
Page 221: Internal Flash Memory Programming Guidelines
Internal Flash Memory Internal Flash Memory Programming Guidelines The following sections describe programming guidelines for the internal flash memory: • “Bringing Internal Flash Memory Out of Reset” on page 6-78 • “Timing Configurations for Setting the Internal Flash Memory in Asynchronous Read Mode”...
Page 222: Bringing Internal Flash Memory Out Of Reset
FLASH_CONTROL enables the flash by bringing it out of reset. Refer to ADSP-BF504, ADSP-BF504F, ADSP-BF506F Embedded Proces- sor Data Sheet for the timing requirements needed to bring the internal flash memory out of reset. A minimum time (listed in the data sheet)
Page 223: Timing Configurations For Setting The Internal Flash Memory In Asynchronous Read Mode
Internal Flash Memory instructions. For example, the code below uses a number of assembly instructions in order to achieve the desired delay: void flash_reset(void) /* Reset the flash */ *pFLASH_CONTROL_CLEAR = FLASH_ENABLE; asm("ssync;nop;nop;nop;nop;nop;nop;nop;"); asm("ssync;nop;nop;nop;nop;nop;nop;nop;"); asm("ssync;nop;nop;nop;nop;nop;nop;nop;"); asm("ssync;nop;nop;nop;nop;nop;nop;nop;"); /* Release flash from reset state */ *pFLASH_CONTROL_SET = FLASH_ENABLE;...
Page 224: Timing Configurations For Setting The Internal Flash Memory For Write Accesses
Internal Flash Memory Programming Guidelines • RAT > 30 ns • HT (for consecutive reads) = 0 ns The recommended timing values to be programmed in the EBIU_AMBCTL register for asynchronous read accesses are: • = ceiling (20 ns / t B0ST SCLK •...
Page 225 Internal Flash Memory The recommended timing values to be programmed in the EBIU_AMBCTL register for asynchronous write accesses are: • = ceiling (20 ns / t B0ST SCLK • = ceiling (45 ns / t B0WAT SCLK • = ceiling (10 ns / t B0HT SCLK In addition to the above timing requirements, a minimum of 25 ns should...
Page 226: Enabling The Program Or Erasure Of Internal Flash Memory Blocks
Internal Flash Memory Programming Guidelines Figure 6-11 shows example asynchronous read and write waveforms for the internal flash. The signal names referenced in the figure are explained Table 6-1 on page 6-2. SETUP READ ACCESS HOLD SETUP WRITE ACCESS HOLD 2 CYCLES 6 CYCLES 1 CYCLE...
Page 227: Configuring Internal Flash Memory For Synchronous Burst Read Mode
Internal Flash Memory page 6-7 for information on flash commands including the block unlock command. Configuring Internal Flash Memory for Synchronous Burst Read Mode In order to operate the internal flash device in synchronous burst mode, both the internal flash device and the EBIU have to be set in synchronous mode.
Page 228: Supported Configuration Register Combinations In Adsp-Bf50Xf Processors
Internal Flash Memory Programming Guidelines  Because the flash device is 2-bytes addressable while the Blackfin processor is 1-byte addressable, the value to be programmed into the flash’s configuration register has to be shifted up by one so it will appear on the Blackfin processor’s address bits [16:1] thus appearing on the flash device’s address bits [15:0].
Page 229: Configuring The Ebiu For Synchronous Read Mode
Internal Flash Memory • through have to be programmed to b#011 • The value to be programmed in the X latency bit field ( CR13 through ) depends on the frequency, as shown in CR11 NOR_CLK Table 6-31. Table 6-31. X Latency Setting Depends on Frequency NOR_CLK Frequency X Latency (in Terms of NOR_CLK Cycles) ...
Page 230 Internal Flash Memory Programming Guidelines • must be programmed depending on the frequency B0ST NOR_CLK selected in the register as shown in the following table: EBIU_FCTL SCLK:NOR_CLK Min Setup Time B0ST Values B0ST Value Supported Recommended 2 : 1 2 SCLK cycles 10,11,00 3 : 1 3 SCLK cycles...
Page 231: Unsupported Programming Practices In Flash
Internal Flash Memory SETUP X-LATENCY HOLD 2 CYCLES 3 BURST CLOCK CYCLES 0 CYCLE CLKOUT ADDR[21:1] HIGH-Z HIGH-Z WAIT HIGH-Z HIGH-Z DQ[15:0] WAIT 15TH 16TH SAMPLED DATA DATA DATA DATA 1 CYLCE SAMPLED SAMPLED SAMPLED SAMPLED BEFORE Figure 6-12. Example Sync Read and Write Waveforms Unsupported Programming Practices in Flash The following programming practices are unsupported by the internal flash memory:...
Page 232: Internal Flash Memory Control Registers
Internal Flash Memory Control Registers • The assembly instruction of the Blackfin processor cannot TESTSET be used with a variable that resides in the internal flash memory. • DMA writes to internal flash memory shall be avoided. • While the internal flash memory is supported by the Blackfin pro- cessor cache, no writes from cache to flash are supported.
Page 233: Register
Internal Flash Memory Using the bits in the register (see Table 6-32) permits con- FLASH_CONTROL trol of the internal flash memory. Table 6-32. Internal Flash Memory Control Register (FLASH_CONTROL) Register Field Name Offset Access Description Enable internal flash memory for FLASH_ENABLE read/write 0 –...
Page 234 Internal Flash Memory Control Registers When the Blackfin processor is in hibernate state, the internal flash mem- ory device is placed in reset state by driving the signal with a logic-low. Refer to “Bringing Internal Flash Memory Out of Reset” on page 6-78 more information on using the bit to reset the internal flash FLASH_ENABLE...
Page 235: Internal Flash Memory Control Set (Flash_Control_Set) Register
Internal Flash Memory Internal Flash Memory Control Set (FLASH_CONTROL_SET) Register Writing to a bit in the register sets the corresponding FLASH_CONTROL_SET bit in the internal flash memory control register. Reads return the internal flash memory control register value. Address Register Name Size Reset Value 0xFFC0 3290...
Page 236 Internal Flash Memory Control Registers 6-92 ADSP-BF50x Blackfin Processor Hardware Reference...
Page 237: Direct Memory Access
Specific Information for the ADSP-BF50x For details regarding the number of DMA controllers for the ADSP-BF50x product, refer to ADSP-BF504, ADSP-BF504F, ADSP-BF506F Embedded Processor Data Sheet. For DMA interrupt vector assignments, refer to Table 4-3 on page 4-19 Chapter 4, “System Interrupts”.
Page 238: Overview And Features
Overview and Features DMA controller behavior for the ADSP-BF50x that differs from the gen- eral information in this chapter can be found in the section “Unique Information for the ADSP-BF50x Processor” on page 7-103. Overview and Features The processor uses DMA to transfer data between memory spaces or between a memory space and a peripheral.
Page 239 Direct Memory Access  SDRAM and SRAM are not available on all products. Refer to “Unique Information for the ADSP-BF50x Processor” on page 7-103 to determine whether it applies to this product. DMA transfers on the processor can be descriptor-based or register-based. Register-based DMA allows the processor to directly program DMA con- trol registers to initiate a DMA transfer.
Page 240: Dma Controller Overview
DMA Controller Overview • 2-D DMA, using an array of 1-word descriptors, specifying only the base DMA address within a common data page • 2-D DMA, using a linked list of 9-word descriptors specifying everything DMA Controller Overview A block diagram of the DMA controller can be found in the “Unique Information for the ADSP-BF50x Processor”...
Page 241: Peripheral Dma
Direct Memory Access The 16-bit DMA core bus (DCB) connects the DMA controller to a dedi- cated port of L1 memory. L1 memory has dedicated DMA ports featuring special DMA buffers to decouple DMA operation. See Blackfin Processor Programming Reference for a description of the L1 memory architecture. The DCB bus operates at core clock ( ) frequency.
Page 242: Memory Dma
DMA Controller Overview The default configuration should suffice in most cases, but there are some cases where remapping the assignment can be helpful because of the DMA channel priorities. When competing for any of the system buses, DMA0 has higher priority than DMA1, and so on. DMA11 has the lowest prior- ity of the peripheral DMA channels.
Page 243 Direct Memory Access buses. Typically, it is used to transfer data between external memory and internal memory. It will also support DMA from the boot ROM on the DEB bus. The FIFO can be used to hold DMA data transferred between two L1 memory locations or between two external memory locations.
Page 244: Handshaked Memory Dma (Hmdma) Mode
DMA Controller Overview destination DMA engine empties it. The FIFO depth allows the burst transfers of the external access bus (EAB) and DMA access bus (DAB) to overlap, significantly improving throughput on block transfers between internal and external memory. Two separate descriptor blocks are required to supply the operating parameters for each MDMA pair, one for the source channel and one for the destination channel.
Page 245: Modes Of Operation
Direct Memory Access asynchronous FIFO-style devices connected to the EBIU port. The Black- fin processor acknowledges a DMA request by a proper number of read or write operations. It is up to the device connected to any of the AMSx strobes to deassert or pulse the request signal and to decrement the num- ber of pending requests accordingly.
Page 246 Modes of Operation • Write the address modifier to the 16-bit register. DMAx_X_MODIFY This is the two’s-complement value added to the address pointer after every transfer. This value must always be initialized as there is no default value. Typically, this register is set to 0x0004 for 32-bit DMA transfers, to 0x0002 for 16-bit transfers, and to 0x0001 for byte transfers.
Page 247: Stop Mode
Direct Memory Access Stop Mode In stop mode, the DMA operation is executed only once. When started, the DMA channel transfers the desired number of data words and stops itself when the transfer is complete. If the DMA channel is no longer used, software should clear the enable bit to disable the otherwise paused DMAEN...
Page 248 Modes of Operation DMAx_Y_COUNT values specify the row and column sizes, where DMAx_X_COUNT must be 2 or greater. The start address and modify values are in bytes, and they must be aligned to a multiple of the DMA transfer word size ( WDSIZE[1:0] ).
Page 249: Examples Of Two-Dimensional Dma
Direct Memory Access Examples of Two-Dimensional DMA Example 1: Retrieve a 16 × 8 block of bytes from a video frame buffer of size (N × M) pixels: DMAx_X_MODIFY = 1 DMAx_X_COUNT = 16 (offset from the end of one row to the start of DMAx_Y_MODIFY = N–15 another) DMAx_Y_COUNT = 8...
Page 250: Descriptor-Based Dma Operation
Modes of Operation Descriptor-based DMA Operation In descriptor-based DMA operation, software does not set up DMA sequences by writing directly into DMA controller registers. Rather, soft- ware keeps DMA configurations, called descriptors, in memory. On demand, the DMA controller loads the descriptor from memory and over- writes the affected DMA registers by its own control.
Page 251: Descriptor List Mode
Direct Memory Access Descriptor List Mode Descriptor list mode is selected by setting the FLOW bit field in the DMA channel’s DMAx_CONFIG register to either 0x6 (small descriptor mode) or 0x7 (large descriptor mode). In either of these modes multiple descrip- tors form a chained list.
Page 252 Modes of Operation memory. The values have the same order as the corresponding MMR addresses. If, for example, a descriptor is fetched in array mode with = 0x5, NDSIZE the DMA controller fetches the 32-bit start address, the DMA configura- tion word, and the values.
Page 253: Mixing Flow Modes
Direct Memory Access Note that every descriptor fetch consumes bandwidth from either the DCB bus or the DEB bus and the external memory interface, so it is best to keep the size of descriptors as small as possible. Mixing Flow Modes mode of a DMA is not a global setting.
Page 254: Functional Description
Functional Description registers are not preset to a default DMAx_X_MODIFY DMAx_Y_MODIFY value at reset. The user may wish to write other DMA registers that might be static dur- ing DMA activity (for example, ). The DMAx_X_MODIFY DMAx_Y_MODIFY contents of indicate which registers, if NDSIZE FLOW DMAx_CONFIG...
Page 255 Direct Memory Access USER WRITES SOME OR ALL DMA PARAMETER REGISTERS, AND THEN WRITES DMA_CONFIG BAD DMA_CONFIG? DMA ERROR DMAEN = 0 TEST DMAEN DI_EN = 0 OR (DI_EN = 1 AND DMA_DONE_IRQ = 1) DMAEN = 1 SET DMA_RUN IN IRQ_STATUS DMA STOPPED.
Page 256 Functional Description NDSIZE = 0 OR NDSIZE > MAX_SIZE* TEST NDSIZE ABORT OCCURS NDSIZE > 0 AND NDSIZE <= MAX_SIZE* READ NDSIZE ELEMENTS OF DESCRIPTOR INTO PARAMETER REGISTERS VIA CURRENT DESCRIPTOR POINTER FLOW = 0 OR 1 CLEAR DFETCH IN IRQ_STATUS DMA TRANSFER BEGINS AND...
Page 257 Direct Memory Access When is written directly by software, the DMA controller DMAx_CONFIG recognizes this as the special startup condition that occurs when starting DMA for the first time on this channel or after the engine has been stopped ( = 0).
Page 258 Functional Description is part of the descriptor, then the value programmed DMACFG DMAx_CONFIG by the MMR access controls only the loading of the first descriptor from memory. The subsequent DMA work operation is controlled by the low byte of the descriptor’s and by the parameter registers loaded from DMACFG the descriptor.
Page 259: Dma Refresh
Direct Memory Access DMA Refresh On completion of a work unit: • The DMA controller completes the transfer of all data between memory and the DMA unit. • If = 1 and = 0 (memory read), the DMA controller selects SYNC a synchronized transition and transfers all data to the peripheral before continuing.
Page 260 Functional Description elements. The high 16 bits of will retain their DMAx_NEXT_DESC_PTR former value. This supports a shorter, more efficient descriptor than the large descriptor list model, which is suitable whenever the application can place the channel’s descriptors in the same 64K byte range of memory.
Page 261: Work Unit Transitions
Direct Memory Access • If = any value but 0 (Stop), the DMA controller begins the FLOW next work unit for that channel, which must contend with other channels for priority on the memory buses. On the first memory transfer of the new work unit, the DMA controller updates the cur- rent registers from the start registers: loaded from DMAx_CURR_ADDR...
Page 262: Dma Transmit And Mdma Source
Functional Description 0. In transmit (memory read) channels, the bit of the last SYNC descriptor prior to the transition controls the transition behavior. In contrast, in receive channels, the bit of the first descriptor SYNC of the next descriptor chain controls the transition. DMA Transmit and MDMA Source In DMA transmit (memory read) and MDMA source channels, the SYNC...
Page 263: Dma Receive
Direct Memory Access  = 0 (continuous transition) on a transmit (memory read) SYNC descriptor, the next descriptor must have the same data word size, read/write direction, and source memory (internal vs. external) as the current descriptor. = 0 selects continuous transition on a work unit in = 0 mode SYNC FLOW...
Page 264 Functional Description descriptors), when the DMA channel is paused. The DMA channel pauses after descriptors with = 0 mode, and may be restarted (for example, FLOW after an interrupt) by writing the channel’s register with DMAx_CONFIG = 1. DMAEN If the bit is 0 in the new work unit’s value, a continuous SYNC...
Page 265: Stopping Dma Transfers
Direct Memory Access  The DMA word size must not change between one descriptor and the next in any DMA receive (memory write) channel within a sin- gle descriptor chain, regardless of the bit setting. In other SYNC words, if a descriptor has = 1 and = 4, 6, or 7, then the FLOW...
Page 266: Dma Errors (Aborts)
Functional Description DMA Errors (Aborts) The DMA controller flags conditions that cause the DMA process to end abnormally (abort). This functionality is provided as a tool for system development and debug to detect DMA-related programming errors. DMA errors (aborts) are detected by the DMA channel module in the cases listed below.
Page 267 Direct Memory Access • A disallowed register write occurred while the channel was run- ning. Only the registers can be DMAx_CONFIG DMAx_IRQ_STATUS written when = 1. DMA_RUN • An address alignment error occurred during any memory access. For example, when register = 1 (16-bit) but DMAx_CONFIG...
Page 268: Dma Control Commands
Functional Description Table 7-2. Legal NDSIZE Values FLOW NDSIZE Note 0 < NDSIZE  7 Descriptor array, no descriptor pointer fetched 0 < NDSIZE  8 Descriptor list, small descriptor pointer fetched 0 < NDSIZE  9 Descriptor list, large descriptor pointer fetched DMA Control Commands Advanced peripherals, such as an Ethernet MAC module, are capable of managing some of their own DMA operations, thus dramatically improv-...
Page 269 Direct Memory Access MDMA channels do not service peripherals and therefore do not support DMA control commands. The DMA control commands are shown in Table 7-3. Table 7-3. DMA Control Commands Code Name Description No operation Restart Restarts the current work unit from the beginning Finish Finishes the current work unit and starts the next Reserved...
Page 270 Functional Description peripheral are granted as soon as new prefetched data is available in the DMA FIFO. The peripheral can thus use the Restart command to re-attempt a failed transmission of a work unit. If a channel programmed for receive (memory write) receives a Restart command, the channel stops writing to memory, discards any data held in its DMA FIFO, and resets its counters and FIFO.
Page 271: Restrictions
Direct Memory Access FIFO reaches an empty state, the channel signals an interrupt (if enabled) and begins fetching the next descriptor (if any). Once the next descriptor has been fetched, the channel initializes its FIFO and then resumes granting DMA requests from the peripheral. •...
Page 272: Receive Restart Or Finish
Functional Description restriction is satisfied. This implies that any work unit which might be managed by commands must have Restart Finish DMAx_CURR_X_COUNT values representing at least five data items. DMAx_CURR_Y_COUNT Particularly if the registers are DMAx_CURR_X_COUNT DMAx_CURR_Y_COUNT programmed to 0 (representing 65,536 transfers, the maximum value) the channel will operate properly for 1-D work units up to 65,531 data items or 2-D work units up to 4,294,967,291 data items.
Page 273: Handshaked Memory Dma Operation
Direct Memory Access senting more data items than the maximum work unit size that the peripheral will encounter. For example, DMAx_CURR_X_COUNT values of 0 allow the channel to operate properly on DMAx_CURR_Y_COUNT 1-D work units up to 65,535 data items and 2-D work units up to 4,294,967,295 data items.
Page 274: Pipelining Dma Requests
Functional Description may request a block transfer before the entire buffer is available by simply taking the minimum transfer time based on wait-state settings into consideration.  The block count defines how many data transfers are performed by the MDMA engine. A single DMA transfer can cause two read or write operations on the EBIU port if the transfer word size is set to 32-bit in the register (...
Page 275 Direct Memory Access registers reload the registers every time HMDMAx_ECINIT HMDMAx_ECOUNT the handshake mode is enabled (when the bit changes from HMDMAEN 0 to 1). If the initial edge count value is 0, the handshake operation starts with a settled request budget. If positive, the engine starts immediately transferring the programmed number (up to 32767) of blocks once enabled, even without detecting any activity on the pins.
Page 276: Hmdma Interrupts
Functional Description the write strobe, but the fast MDMA engine would read out the FIFO quickly and stall soon if the FIFO was not promptly filled with new data. Streaming applications can balance the FIFO so that the producer is never held off by a full FIFO and the consumer is never held by an empty FIFO.
Page 277: Dma Performance
Direct Memory Access interrupt status bits require a write-1-to-clear operation to cancel the interrupt request. interrupt signals that a complete MDMA block, as block done defined by the register, has been transferred (when the HMDMAx_BCINIT register decrements to zero). While the bit enables HMDMAx_BCOUNT BDIE...
Page 278: Dma Throughput
Functional Description • How heavily is the DMA controller competing with the core for on-chip and off-chip resources? • How often do competing DMA channels require the bus systems to alter direction? • How often do competing DMA or core accesses cause the SDRAM to open different pages? •...
Page 279 Direct Memory Access When the traffic on all DMA channels is taken in the aggregate: • Transfers between the peripherals and the DMA unit have a maxi- mum rate of one 16-bit transfer per system clock. • Transfers between the DMA unit and internal memory (L1) have a maximum rate of one 16-bit transfer per system clock.
Page 280 Functional Description • Descriptor fetches consume one DMA memory cycle per 16-bit word read from memory, but do not delay transfers on the DAB bus. • Initialization of a DMA channel stalls DMA activity for one cycle. This occurs when changes from 0 to 1 or when the DMAEN SYNC...
Page 281: Memory Dma Timing Details
Direct Memory Access DMA in s (which is typically seven for internal transfers and six for SCLK external transfers). Memory DMA Timing Details When the destination register is written, MDMA operation DMAx_CONFIG starts after a latency of three cycles. SCLK If either MDMA channel has been selected to use descriptors, the descrip- tors are fetched from memory.
Page 282 Functional Description is not too large a fraction of the total, then all peripherals’ requests should be granted as required. Occasionally, instantaneous DMA traffic might exceed the available band- width, causing congestion. This may occur if L1 or external memory is temporarily stalled, perhaps for an SDRAM page swap or a cache line fill.
Page 283: Memory Dma Priority And Scheduling
Direct Memory Access When one or more DMA channels express an urgent memory request, two events occur: • All non-urgent memory requests are decreased in priority by 32, guaranteeing that only an urgent request will be granted. The urgent requests compete with each other, if there is more than one, and directional preference among urgent requests is observed.
Page 284 Functional Description If this field is set to 0, then MDMA is scheduled by fixed priority. MDMA stream 0 takes precedence over MDMA stream 1 whenever stream 0 is ready to perform transfers. Since an MDMA stream is typically capable of transferring data on every available cycle, this could cause MDMA stream 1 traffic to be delayed for an indefinite time until any and all MDMA stream 0 operations are completed.
Page 285: Traffic Control
Direct Memory Access ready to perform a transfer, then no transfer is performed, and the stream selection unlocks and becomes free again on the next cycle. If round-robin operation is used when only one MDMA stream is active, one idle cycle will occur for each P MDMA data cycles, slightly lowering the bandwidth by a factor of 1/(P+1).
Page 286 Functional Description mechanism controlled by the registers. This DMA_TC_PER DMA_TC_CNT mechanism performs the optimization without real-time processor inter- vention and without the need to program transfer bursts into the DMA work unit streams. Traffic can be independently controlled for each of the three buses (DAB, DCB, and DEB) with simple counters.
Page 287: Programming Model
Direct Memory Access Programming Model Several synchronization and control methods are available for use in devel- opment of software tasks which manage peripheral DMA and memory DMA (see also “Memory DMA” on page 7-6). Such software needs to be able to accept requests for new DMA transfers from other software tasks, integrate these transfers into existing transfer queues, and reliably notify other tasks when the transfers are complete.
Page 288 Programming Model has its own distinct interrupt, interaction among the interrupts of differ- ent peripherals is much simpler to manage. Due to DMA FIFOs and DMA/memory pipelining, polling of the , or DMAx_CURR_ADDR DMAx_CURR_DESC_PTR DMAx_CURR_X_COUNT registers is not recommended for precisely synchroniz- DMAx_CURR_Y_COUNT ing DMA with data processing.
Page 289: Single-Buffer Dma Transfers
Direct Memory Access length and the DMA/memory pipeline length are added, an estimate can be made of the maximum number of incomplete memory operations in progress at one time. This value is a maximum because the DMA/memory pipeline may include traffic from other DMA channels. For example, assume a peripheral DMA channel is transferring a work unit of 100 data elements into internal memory and its register reads a value of 60 remaining elements, so...
Page 290: Continuous Transfers Using Autobuffering
Programming Model user may choose to write all the MMR registers directly from software, ending with the write to the register. DMAx_CONFIG The simplest way to signal completion of DMA is by an interrupt. This is selected by the bit in the register, and by the necessary DI_EN DMAx_CONFIG...
Page 291 Direct Memory Access For example, two 512-word sub-buffers inside a 1K-word buffer could be used to receive 16-bit peripheral data with these settings: = buffer base address DMAx_START_ADDR = 0x10D7 ( = 1, = 1, = 1, DMAx_CONFIG FLOW DI_EN DI_SEL = 1, = 1,...
Page 292: Descriptor Structures
Programming Model The synchronization core might read to determine DMAx_Y_COUNT which sub-buffer is currently being transferred, and then allow one full sub-buffer to account for pipelining. For example, if a read of shows a value of 3, then the software should assume DMAx_Y_COUNT that sub-buffer 3 is being transferred, but some portion of sub-buf- fer 2 may not yet be received.
Page 293: Descriptor Queue Management
Direct Memory Access It is important to remember the meaning of the various fields in the descriptor elements when building a list or array of DMA DMAx_CONFIG descriptors. In particular: • The lower byte of specifies the DMA transfer to be DMAx_CONFIG performed by the current descriptor (for example 2-D inter- rupt-enable mode)
Page 294: Descriptor Queue Using Interrupts On Every Descriptor
Programming Model circular structure. In this case, the members of each NDPH NDPL descriptor could even be written once at startup and skipped over as each descriptor’s new contents are written. The recommended method for synchronization of a descriptor queue is through the use of an interrupt.
Page 295: Descriptor Queue Using Minimal Interrupts
Direct Memory Access If the counts are unequal, the software instead modifies the next-to-last descriptor’s value so that its upper half ( DMAx_CONFIG FLOW NDSIZE now describes the newly queued descriptor. This operation does not dis- rupt the DMA channel, provided the rest of the descriptor data structure is initialized in advance.
Page 296 Programming Model When each new DMA request is processed, the software’s non-interrupt code fills in a new descriptor’s contents and adds it to the waiting portion of the queue. The descriptor’s word should have a value DMAx_CONFIG FLOW of zero. If more than one request is received before the DMA queue com- pletion interrupt occurs, the non-interrupt code should queue later descriptors, forming a waiting portion of the queue that is disconnected from the active portion of the queue being processed by the DMA unit.
Page 297: Software-Triggered Descriptor Fetches
Direct Memory Access active queue. The interrupt handler should then pass a message back to the non-interrupt software indicating the location of the last descriptor accepted into the active queue. If, on the other hand, the interrupt han- dler reads its mailbox and finds a value of zero, indicating DMAx_CONFIG there is no more work to perform, then it should pass an appropriate mes-...
Page 298 Programming Model and force the DMA controller to fetch the next descriptor. To accomplish this, the software writes a value with the bit set and with proper val- DMAEN ues in the fields into the configuration register. The next FLOW NDSIZE descriptor is fetched if equals 0x4, 0x6, or 0x7.
Page 299: Dma Registers
Direct Memory Access If all fields in a descriptor chain have the fields set DMACFG FLOW NDSIZE to zero, the individual DMA sequences do not start until triggered by soft- ware. This is useful when the DMAs need to be synchronized with other events in the system, and it is typically performed by interrupt service rou- tines.
Page 300: Dma Channel Registers
DMA Registers DMA Channel Registers A processor features up to twelve peripheral DMA channels and two chan- nel pairs for memory DMA. All channels have an identical set of registers as summarized in Table 7-4. Table 7-4 lists the generic names of the DMA registers. For each register, the table also shows the MMR offset, a brief description of the register, the register category, and where applicable, the corresponding name for the data element in a DMA descriptor.
Page 301 Direct Memory Access Table 7-4. Generic Names of the DMA Memory-Mapped Registers (Cont’d) Generic MMR MMR Description Register Name of Offset Name Category Corresponding Descriptor Element in Memory 0x28 Interrupt status register con- Control/ IRQ_STATUS tains completion and DMA Status error interrupt status and channel state (run/fetch/paused)
Page 302 DMA Registers  The generic MMR names shown in Table 7-4 are not actually mapped to resources in the processor. For convenience, discussions in this chapter use generic (non-peripheral specific) DMA and memory DMA register names. DMA channel registers fall into three categories. •...
Page 303: Dma Peripheral Map Registers
Direct Memory Access DMA Peripheral Map Registers (DMAx_PERIPHERAL_MAP/ MDMA_yy_PERIPHERAL_MAP) Each DMA channel’s DMAx_PERIPHERAL_MAP register contains bits that: • Map the channel to a specific peripheral • Identify whether the channel is a peripheral DMA channel or a memory DMA channel DMA Peripheral Map Registers (DMAx_PERIPHERAL_MAP/MDMA_yy_PERIPHERAL_MAP) R/W prior to enabling channel;...
Page 304: Dma Configuration Registers (Dmax_Config/Mdma_Yy_Config)
DMA Registers DMA Configuration Registers (DMAx_CONFIG/MDMA_yy_CONFIG) The DMAx_CONFIG register, shown in Figure 7-6, is used to set up DMA parameters and operating modes. Writing the DMAx_CONFIG register while DMA is already running will cause a DMA error unless writ- ing with the DMAEN bit set to 0. DMA Configuration Registers (DMAx_CONFIG/MDMA_yy_CONFIG) R/W prior to enabling channel;...
Page 305 Direct Memory Access The fields of the register are used to set up DMA parameters DMAx_CONFIG and operating modes. • (next operation). This field specifies the type of DMA FLOW[2:0] transfer to follow the present one. The flow options are: 0x0 - stop.
Page 306 DMA Registers 0x7 - descriptor list (large model) mode. This mode fetches a descriptor from memory that includes , thus allowing NDPH NDPL maximum flexibility in locating descriptors in memory. • (flex descriptor size). This field specifies the number NDSIZE[3:0] of descriptor elements in memory to load.
Page 307 Direct Memory Access • (DMA mode). This bit specifies whether DMA mode DMA2D involves only (one-dimensional DMAx_X_COUNT DMAx_X_MODIFY DMA) or also involves DMAx_Y_COUNT DMAx_Y_MODIFY (two-dimensional DMA). • (transfer word size). The DMA engine supports trans- WDSIZE[1:0] fers of 8-, 16-, or 32-bit items. Each request/grant results in a single memory access (although two cycles are required to transfer 32-bit data through a 16-bit memory port or through the 16-bit DMA access bus).
Page 308 DMA Registers DMA Interrupt Status Registers (DMAx_IRQ_STATUS/MDMA_yy_IRQ_STATUS) The DMAx_IRQ_STATUS register, shown in Figure 7-7, contains bits that record whether the DMA channel: • Is enabled and operating, enabled but stopped, or disabled. • Is fetching data or a DMA descriptor. •...
Page 309 Direct Memory Access The processor supports a flexible interrupt control structure with three interrupt sources: • Data driven interrupts (see Table 7-5) • Peripheral error interrupts • DMA error interrupts (for example, bad descriptor or bus error) Separate interrupt request (IRQ) levels are allocated for data, peripheral error, and DMA error interrupts.
Page 310: Dma Interrupt Status Registers (Dmax_Irq_Status/Mdma_Yy_Irq_Status)
DMA Registers DMA Interrupt Status Registers (DMAx_IRQ_STATUS/MDMA_yy_IRQ_STATUS) 15 14 13 12 11 10 Reset = 0x0000 DMA_RUN (DMA Channel Running) - RO DMA_DONE (DMA Comple- tion Interrupt Status) - W1C This bit is set to 1 automatically when 0 - No interrupt is being the DMAx_CONFIG register is written asserted for this channel 0 - This DMA channel is disabled, or it...
Page 311 Direct Memory Access of each channel can be read to identify the channel that caused the DMA error interrupt.  Note the interrupt indicators are DMA_DONE DMA_ERR write-one-to-clear (W1C).  When switching a peripheral from DMA to non-DMA mode, the peripheral’s interrupts should be disabled during the mode switch (via the appropriate peripheral register or register) so...
Page 312 DMA Registers DMA Current Address Registers (DMAx_CURR_ADDR/MDMA_yy_CURR_ADDR) The 32-bit register shown in Figure 7-9, contains the DMAx_CURR_ADDR present DMA transfer address for a given DMA session. On the first mem- ory transfer of a DMA work unit, the register is loaded DMAx_CURR_ADDR from the register, and it is incremented as each transfer...
Page 313 Direct Memory Access DMA Inner Loop Count Registers (DMAx_X_COUNT/MDMA_yy_X_COUNT) R/W prior to enabling channel; RO after enabling channel 15 14 13 12 11 10 Reset = Undefined X_COUNT[15:0] (Inner Loop Count) The number of elements to transfer (1-D); the number of rows in the inner loop (2-D) Figure 7-10.
Page 314 DMA Registers DMA Current Inner Loop Count Registers (DMAx_CURR_X_COUNT/ MDMA_yy_CURR_X_COUNT) R/W prior to enabling channel; RO after enabling channel 15 14 13 12 11 10 Reset = Undefined CURR_X_COUNT[15:0] (Current Inner Loop Count) Loaded by X_COUNT at the beginning of each DMA session (1-D DMA), or at the beginning of each row (2-D DMA)
Page 315 Direct Memory Access DMA Inner Loop Address Increment Registers (DMAx_X_MODIFY/MDMA_yy_X_MODIFY) R/W prior to enabling channel; RO after enabling channel 15 14 13 12 11 10 Reset = Undefined X_MODIFY[15:0] (Inner Loop Address Increment) Stride (in bytes) to take after each decrement of CURR_X_COUNT Figure 7-12.
Page 316 DMA Registers DMA Current Outer Loop Count Registers (DMAx_CURR_Y_COUNT/ MDMA_yy_CURR_Y_COUNT) register, used only in 2-D mode, holds the num- DMAx_CURR_Y_COUNT ber of full or partial rows (outer loops) remaining in the current work unit. See Figure 7-14. On the first memory transfer of each DMA work unit, it is loaded with the value of the register.
Page 317 Direct Memory Access  is specified in bytes, regardless of the DMA transfer DMAx_Y_MODIFY size. DMA Outer Loop Address Increment Registers (DMAx_Y_MODIFY/ MDMA_yy_Y_MODIFY) R/W prior to enabling channel; RO after enabling channel 15 14 13 12 11 10 Reset = Undefined Y_MODIFY[15:0] (Outer Loop Address Increment)
Page 318 DMA Registers In descriptor array mode, the next descriptor pointer register is disre- garded, and fetching is controlled only by the DMAx_CURR_DESC_PTR register. DMA Next Descriptor Pointer Registers (DMAx_NEXT_DESC_PTR/MDMA_yy_NEXT_DESC_PTR) R/W prior to enabling channel; RO after enabling channel 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset = Undefined Next Descriptor...
Page 319: Hmdma Registers
Direct Memory Access  For descriptor array mode ( = 4), this register, and not the FLOW register, must be programmed by MMR DMAx_NEXT_DESC_PTR access before starting DMA operation. DMA Next Descriptor Pointer Registers (DMAx_NEXT_DESC_PTR/MDMA_yy_NEXT_DESC_PTR) R/W prior to enabling channel; RO after enabling channel 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset = Undefined...
Page 320 DMA Registers field is used to control the priority of the MDMA channel DRQ[1:0] when the HMDMA is disabled, that is, when handshake control is not being used (see Table 7-6). Table 7-6. DRQ[1:0] Values DRQ[1:0] Priority Description Disabled The MDMA request is disabled. Enabled/S Normal MDMA channel priority.
Page 321 Direct Memory Access Handshake MDMA Control Registers (HMDMAx_CONTROL) 15 14 13 12 11 10 Reset = 0x0200 HMDMAEN (Handshake MDMA Enable) 0 - Disable handshake BDI (Block Done Operation Interrupt Generated) 1 - Enable handshake - W1C Operation 0 - Block done interrupt REP (HMDMA Request Polarity) not generated 0 - Increment ECOUNT on...
Page 322 DMA Registers Handshake MDMA Initial Block Count Registers (HMDMAx_BCINIT) register, shown in Figure 7-19, holds the number of HMDMAx_BCINIT transfers to do per edge of the control signal. DMARx Handshake MDMA Initial Block Count Registers (HMDMAx_BCINIT) 15 14 13 12 11 10 Reset = 0x0000 BCINIT[15:0] (Initial Block Count)
Page 323: Handshake Mdma Current Block Count Registers (Hmdmax_Bcount)
Direct Memory Access Handshake MDMA Current Block Count Register (HMDMAx_BCOUNT) 15 14 13 12 11 10 Reset = 0x0000 BCOUNT[15:0] (Transfers Remaining for Current Edge) Figure 7-20. Handshake MDMA Current Block Count Registers Handshake MDMA Current Edge Count Registers (HMDMAx_ECOUNT) register, shown in Figure 7-21, holds a signed number...
Page 324: Handshake Mdma Initial Edge Count Registers
DMA Registers Handshake MDMA Current Edge Count Register (HMDMAx_ECOUNT) 15 14 13 12 11 10 Reset = 0x0000 ECOUNT[15:0] (Edges Remaining to be Serviced) Figure 7-21. Handshake MDMA Current Edge Count Registers Handshake MDMA Initial Edge Count Registers (HMDMAx_ECINIT) register, shown in Figure 7-22, holds a signed number HMDMAx_ECINIT...
Page 325: Dma Traffic Control Registers
Direct Memory Access Handshake MDMA Edge Count Urgent Registers (HMDMAx_ECURGENT) 15 14 13 12 11 10 Reset = 0xFFFF UTHE[15:0] (Urgent Threshold) Figure 7-23. Handshake MDMA Edge Count Urgent Registers Handshake MDMA Edge Count Overflow Interrupt Registers (HMDMAx_ECOVERFLOW) register, shown in Figure 7-24, holds the inter- HMDMAx_ECOVERFLOW...
Page 326: Dma_Tc_Per Register
DMA Registers DMA_TC_PER Register DMA Traffic Control Counter Period Register (DMA_TC_PER) 15 14 13 12 11 10 Reset = 0x0000 MDMA_ROUND_ROBIN_PERIOD[4:0] DCB_TRAFFIC_PERIOD[3:0] 0000 - No DCB bus transfer Maximum length of MDMA round grouping performed robin bursts. If not zero, any MDMA Other - Preferred length of unidi- stream which receives a grant is rectional bursts on the DCB bus...
Page 327 Direct Memory Access field shows the current transfer count MDMA_ROUND_ROBIN_COUNT remaining in the MDMA round-robin period. It initializes to whenever is written, whenever a MDMA_ROUND_ROBIN_PERIOD DMA_TC_PER different MDMA stream is granted, or whenever every MDMA stream is idle. It then counts down to 0 with each MDMA transfer. When this count decrements from 1 to 0, the next available MDMA stream is selected.
Page 328: Programming Examples
Programming Examples direction DCB accesses are treated preferentially. When this count decre- ments from 1 to 0, the opposite direction DCB access is treated preferentially, which may result in a direction change. When this count is 0 and a DCB bus access occurs, the count is reloaded from to begin a new burst.
Page 329 Direct Memory Access Listing 7-1. Register-Based 2-D Memory DMA #include <defBF527.h>/*For ADSP-BF527 product, as an example.*/ #define X 5 #define Y 6 .section L1_data_a; .byte2 aSource[X*Y] = 7, 13, 19, 25, 8, 14, 20, 26, 9, 15, 21, 27, 4, 10, 16, 22, 28, 5, 11, 17, 23, 29, 6, 12, 18, 24, 30;...
Page 330 Programming Examples Listing 7-2. Two-Dimensional Memory DMA Setup Example memdma_setup: [--sp] = r7; /* setup 1D source DMA for 16-bit transfers */ r7.l = lo(aSource); r7.h = hi(aSource); [p0 + MDMA_S0_START_ADDR - MDMA_S0_CONFIG] = r7; r7.l = 2; w[p0 + MDMA_S0_X_MODIFY - MDMA_S0_CONFIG] = r7; r7.l = X * Y;...
Page 331: Initializing Descriptors In Memory
Direct Memory Access Listing 7-3. Polling DMA Status memdma_wait: [--sp] = r7; memdma_wait.test: r7 = w[p0 + MDMA_D0_IRQ_STATUS - MDMA_S0_CONFIG] (z); CC = bittst (r7, bitpos(DMA_DONE)); if !CC jump memdma_wait.test; r7 = DMA_DONE (z); w[p0 + MDMA_D0_IRQ_STATUS - MDMA_S0_CONFIG] = r7; r7 = [sp++];...
Page 332 Programming Examples Listing 7-4. Two Descriptors in Small List Flow Mode .section sdram; .byte2 arrBlock1[0x400]; .byte2 arrBlock2[0x800]; .section L1_data_a; .byte2 descBlock1 = lo(descBlock2); .var descBlock1.addr = arrBlock1; .byte2 descBlock1.cfg = FLOW_SMALL|NDSIZE_5|WDSIZE_16|DMAEN; .byte2 descBlock1.len = length(arrBlock1); descBlock1.end: .byte2 descBlock2 = lo(descBlock1); .var descBlock2.addr = arrBlock2;...
Page 333 Direct Memory Access } dma_desc_arr; typedef struct { void *pNext; void *pStart; short dConfig; short dXCount; short dXModify; short dYCount; short dYModify; } dma_desc_list; #endif // _LANGUAGE_C #endif // __INCLUDE_DESCRIPTORS__ Note that near pointers are not natively supported by the C language and, thus, pointers are always 32 bits wide.
Page 334: Software-Triggered Descriptor Fetch Example
Programming Examples 0, 0 /* unused values */ .struct dma_desc_list descBlock4 = { descBlock3, arrBlock4, FLOW_LARGE | NDSIZE_7 | DI_EN | WDSIZE_32 | DMAEN, length(arrBlock4), 4, 0, 0 /* unused values */ Software-Triggered Descriptor Fetch Example Listing 7-7 demonstrates a large list of descriptors that provide FLOW (stop mode) configuration.
Page 335 Direct Memory Access .byte2 arrDest2[2*N]; .struct dma_desc_list descSource1 = { descSource2, arrSource1, WDSIZE_16 | DMAEN, length(arrSource1), 2, 0, 0 /* unused values */ .struct dma_desc_list descSource2 = { descSource3, arrSource2, FLOW_LARGE | NDSIZE_7 | WDSIZE_16 | DMAEN, length(arrSource2), 2, 0, 0 /* unused values */ .struct dma_desc_list descSource3 = { descSource1, arrSource3,...
Page 336 Programming Examples _main: /* write descriptor address to next descriptor pointer */ p0.h = hi(MDMA_S0_CONFIG); p0.l = lo(MDMA_S0_CONFIG); r0.h = hi(descDest1); r0.l = lo(descDest1); [p0 + MDMA_D0_NEXT_DESC_PTR - MDMA_S0_CONFIG] = r0; r0.h = hi(descSource1); r0.l = lo(descSource1); [p0 + MDMA_S0_NEXT_DESC_PTR - MDMA_S0_CONFIG] = r0; /* start first work unit */ r6.l = FLOW_LARGE|NDSIZE_7|WDSIZE_16|DMAEN;...
Page 337: Handshaked Memory Dma Example
Direct Memory Access Handshaked Memory DMA Example The functional block for the handshaked MDMA operation can be con- sidered completely separately from the MDMA channels themselves. Therefore the following HMDMA setup routine can be combined with any of the MDMA examples discussed above. Be sure that the HMDMA module is enabled before the MDMA channels.
Page 338 Programming Examples w[p1] = r0; /* enable for rising edges */ p1.l = lo(HMDMA1_CONTROL); r2.l = REP | HMDMAEN; w[p1] = r2; If the HMDMA is intended to copy from internal memory to external devices, the above setup is sufficient. If, however, the data flow is from outside the processor to internal memory, then this small issue must be considered—the HMDMA only controls the destination channel of the memory DMA.
Page 339: Unique Information For The Adsp-Bf50X Processor
Direct Memory Access w[p1] = r0; w[p1] = r2; If the polling operation shown in Listing 7-9 is too expensive, an interrupt version of it can be implemented by using the HMDMA overflow feature. Temporarily set the register to eight. HMDMAx_OVERFLOW Unique Information for the ADSP-BF50x Processor...
Page 340 Unique Information for the ADSP-BF50x Processor CCLK SCLK DMA TRAFFIC CONTROL IRQ 1 MDMA 0 SOURCE CONTROL FIFO IRQ 42 MDMA 0 DESTINATION CONTROL MDMA 1 SOURCE CONTROL FIFO IRQ 43 MDMA 1 DESTINATION CONTROL IRQ 25 DMA 11 CONTROL FIFO PMAP IRQ 24...
Page 341: Static Channel Prioritization
Direct Memory Access Static Channel Prioritization The default DMA channel priority and mapping shown in Table 7-7 be changed by altering the 4-bit PMAP field in the DMAx_PERIPHERAL_MAP registers for the peripheral DMA channels. Table 7-7. Priority and Default Mapping of Peripheral to DMA DMA Channel PMAP Default Value Peripheral Mapped by Default Priority Highest...
Page 342 Unique Information for the ADSP-BF50x Processor 7-106 ADSP-BF50x Blackfin Processor Hardware Reference...
Page 343: Dynamic Power Management
8 DYNAMIC POWER MANAGEMENT This chapter describes the dynamic power management functionality of the Blackfin processor and includes the following sections: • “Phase Locked Loop and Clock Control” • “Dynamic Power Management Controller” on page 8-7 • “Operating Modes” on page 8-8 •...
Page 344: Pll Overview
Phase Locked Loop and Clock Control DMA Access Bus (DAB), External Access Bus (EAB), and the external bus interface unit (EBIU).  These buses run at the PLL frequency divided by 1–15 ( SCLK domain). Using the parameter of the PLL divide register, SSEL select a divider value that allows these buses to run at or below the maximum...
Page 345 Dynamic Power Management SCLK CLKIN SSEL [3:0} CLKIN LOOP ÷1 OR ÷2 GATE SCLK ÷1,..., ÷15 FILTER PDWN DEEP SLEEP POWERDOWN (CCLK AND SCLK OFF) ÷1, ÷2, ÷4, GATE CCLK ×1,..., ×64 OR ÷8 OUTPUT CLOCK PHASE LOCKED LOOP GENERATOR (CLOCK DIVIDE AND MUX) MSEL [5:0] STOPCK...
Page 346: Pll Clock Multiplier Ratios
Phase Locked Loop and Clock Control intermediate clock from which the core clock ( ) and system clock CCLK ) are derived. SCLK PLL Clock Multiplier Ratios The PLL control register ( ) governs the operation of the PLL. For PLL_CTL details about the register, see...
Page 347: Core Clock/System Clock Ratio Control
Dynamic Power Management Table 8-1. MSEL Encodings (Cont’d) Signal name VCO Frequency MSEL[5:0] DF = 0 DF = 1 31.5x The PLL control ( ) register controls operation of the PLL (see PLL_CTL Figure 8-4 on page 8-21). Note that changes to the register do PLL_CTL not take effect immediately.
Page 348 Phase Locked Loop and Clock Control Unlike writing the register, the register can be pro- PLL_CTL PLL_DIV grammed at any time to change the divide values without CCLK SCLK entering the PLL programing sequence. Table 8-2. Core Clock Ratio Signal Name Divider Ratio Example Frequency Ratios (MHz) CSEL[1:0]...
Page 349: Dynamic Power Management Controller
Dynamic Power Management When changing clock frequencies in the PLL, the PLL requires time to stabilize and lock to the new frequency. The PLL lock count ) register defines the number of cycles that occur PLL_LOCKCNT CLKIN before the processor sets the bit in the register.
Page 350: Operating Modes
Dynamic Power Management Controller Operating Modes The processor works in four operating modes, each with unique perfor- mance and power saving benefits. Table 8-4 summarizes the operational characteristics of each mode. Table 8-4. Operational Characteristics Operating Power CCLK SCLK Allowed Mode Savings Status...
Page 351: Active Mode
Dynamic Power Management full speed. The system clock ( ) frequency is determined by the SCLK SSEL specified ratio to VCO. DMA access is available to L1 and external mem- ories. From full-on mode, the processor can transition directly to active, sleep, or deep sleep modes, as shown in Figure 8-2 on page 8-12.
Page 352: Deep Sleep Mode
Dynamic Power Management Controller  bit is not a status bit and is therefore unmodified by STOPCK hardware when the wakeup occurs. Software must explicitly clear in the next write to to avoid going back into sleep STOPCK PLL_CTL mode. Deep Sleep Mode Deep sleep mode maximizes power savings by disabling the PLL, CCLK...
Page 353: Hibernate State
Dynamic Power Management Hibernate State For lowest possible power dissipation, this state allows the internal supply ) to be powered down by the external regulator, while keeping DDINT the I/O supply (V ) running. Although not strictly an operating DDEXT mode like the four modes detailed above, it is illustrative to view it as such in the diagram of Figure...
Page 354 Dynamic Power Management Controller Sleep WAKEUP & STOPCK = 1 & STOPCK = 1 & BYPASS = 0 PDWN = 0 PDWN = 0 WAKEUP & BYPASS = 1 BYPASS = 0 & PLL_OFF = 0 & STOPCK = 0 & PDWN = 0 Full On Active BYPASS = 1 &...
Page 355 Dynamic Power Management In addition to the mode transitions shown in Figure 8-2, the PLL can be modified while in active operating mode. Changes to the PLL do not take effect immediately. As with operating mode transitions, the PLL program- ming sequence must be executed for these changes to take effect (see “Programming Operating Mode Transitions”...
Page 356: Programming Operating Mode Transitions
Dynamic Power Management Controller  Attempting to cause mode transitions other than those shown in Table 8-6 causes unpredictable behavior. Table 8-6. Allowed Operating Mode Transitions Current Mode Full-On Active Sleep Deep Sleep New Mode Full On – Allowed Allowed Allowed Active Allowed...
Page 357 Dynamic Power Management than the DPMC, from waking up the core from the state. If the lock IDLE counter expires, the PLL issues an interrupt, and the code execution con- tinues the instruction after the instruction. Therefore, the system is IDLE in the new state by the time the routine returns.
Page 358: Dynamic Supply Voltage Control
Dynamic Power Management Controller If no operating mode transition is programmed, the PLL generates a wake-up signal, and the routine returns. bfrom_SysControl() Dynamic Supply Voltage Control In addition to clock frequency control, the processor's core is capable of running at different voltage levels. As power dissipation is proportional to the voltage squared, significant power reductions can be accomplished when lower voltages are used.
Page 359 Dynamic Power Management With an external voltage regulator, this sequence must be reproduced in the program code by the user. The register cannot be used in PLL_LOCKCNT this case, but the value is still needed for calculating the required delay. A larger value may be necessary for changing voltages than PLL_LOCKCNT...
Page 360: Powering Down The Core (Hibernate State)
Dynamic Power Management Controller value. That in turn will set the bit, which should be considered the VSAT end of your “wait” state for the voltage regulator to settle. Powering Down the Core (Hibernate State) The external regulator can be signaled to shut off V using the DDINT signal.
Page 361: Pll And Vr Registers
Dynamic Power Management Powering down V does not affect V . While V is still DDINT DDEXT DDEXT applied to the processor, external pins are maintained at a three-state level unless specified otherwise. To signal the external regulator to power down V DDINT 1.
Page 362: Pll_Div Register
PLL and VR Registers Table 8-7 shows the functions of the PLL/VR registers. Table 8-7. PLL/VR Register Mapping Register Name Function Notes For More Information See: PLL_CTL PLL control register Requires reprogram- Figure 8-4 on page 8-21 ming sequence when written PLL_DIV PLL divisor register...
Page 363: Pll_Ctl Register
Dynamic Power Management PLL_CTL Register PLL Control Register (PLL_CTL) 15 14 13 12 11 10 0xFFC0 0000 Reset = 0x0C80 MSEL[5:0] DF (Divide Frequency) (Multiplier Select) 0 - Pass CLKIN to PLL 1 - Pass CLKIN/2 to PLL See CLKIN/VCO multiplication factors PLL_OFF 0 - Enable control of PLL...
Page 364: Pll_Lockcnt Register
PLL and VR Registers PLL_LOCKCNT Register PLL Lock Count Register (PLL_LOCKCNT) 15 14 13 12 11 10 0xFFC0 0010 Reset = 0x0200 LOCKCNT[15:0] Number of SCLK cycles before PLL Lock Count timer expires. Figure 8-6. PLL Lock Count Register VR_CTL Register Voltage Regulator Control Register (VR_CTL) 15 14 13 12 11 10 Reset = 0x30B0...
Page 365: System Control Rom Function
Dynamic Power Management The external clock select ( ) control bit configures the EXTCLK_SEL EXTCLK pin to output either the SCLK frequency (called ) or to output an CLKOUT input buffered CLKIN frequency (called ). When configured to CLKBUF output SCLK ( ), the pin acts as a reference signal in many CLKOUT...
Page 366 System Control ROM Function  The system control ROM function does not verify the correctness of the forwarded arguments. Therefore, it is up to the programmer to choose the correct values. C prototype: u32 bfrom_SysControl(u32 dActionFlags, ADI_SYSCTRL_VALUES *pSysCtrlSettings, void *reserved); The first argument ( ) to the system control ROM func- u32 dActionFlags...
Page 367: Programming Model
Dynamic Power Management typedef struct u16 uwVrCtl; u16 uwPllCtl; u16 uwPllDiv; u16 uwPllLockCnt; u16 uwPllStat; } ADI_SYSCTRL_VALUES; The third argument to the system control ROM function is reserved and should be kept zero (NULL pointer).  The system control ROM function executes the correct steps and programming sequence for the Dynamic Power Management Sys- tem of the Blackfin processor.
Page 368: Accessing The System Control Rom Function In Assembly
System Control ROM Function registers that should be modified and have valid data in the respective variables: ADI_SYSCTRL_VALUES ADI_SYSCTRL_VALUES write; write.uwPllCtl = 0x1480; write.uwPllDiv = 0x0004; bfrom_SysControl (SYSCTRL_WRITE | SYSCTRL_PLLCTL |SYSCTRL_PLLDIV, &write, NULL); Accessing the System Control ROM Function in Assembly The assembler supports C structs, which is required to import the file bfrom.h:...
Page 369 Dynamic Power Management P5.L = lo(dpm->uwPllDiv); R7 = 0x0004 (z); w[P5] = R7; P5.L = lo(dpm->uwPllLockCnt); R7 = 0x0200 (z); w[P5] = R0; The function u32 bfrom_SysControl(u32 dActionFlags, can be ADI_SYSCTRL_VALUES *pSysCtrlSettings, void *reserved); accessed by . Following the C/C++ run-time environ- BFROM_SYSCONTROL ment conventions, the parameters passed are hold by the data registers , and...
Page 370 System Control ROM Function P5.L = lo(BFROM_SYSCONTROL); call(P5); SP += 12; (R7:0,P5:0) = [SP++]; unlink; rts; The processor’s internal scratchpad memory can be used as an alternative for taking a C struct. Therefore, the stack/frame pointer must be loaded and passed. /* 10 = sizeof(ADI_SYSCTRL_VALUES).
Page 371: Programming Examples
Dynamic Power Management w[FP+-sizeof(ADI_SYSCTRL_VALUES)+offse- tof(ADI_SYSCTRL_VALUES,uwPllLockCnt)] = R7; R0 = SYSCTRL_WRITE SYSCTRL_VRCTL SYSCTRL_EXTVOLTAGE | SYSCTRL_PLLCTL SYSCTRL_PLLDIV R1 = FP; R1 += -sizeof(ADI_SYSCTRL_VALUES); R2 = 0; P5.H = hi(BFROM_SYSCONTROL); P5.L = lo(BFROM_SYSCONTROL); call(P5); SP += 12; (R7:0,P5:0) = [SP++]; unlink; rts; Programming Examples The following code examples illustrate how to use the system control ROM function to effect various operating mode transitions.
Page 372 Programming Examples Some setup code has been removed for clarity, and the following assump- tions are made. • PLL control ( ) register setting: 0x0A80 PLL_CTL • PLL divider ( ) register setting: 0x0004 PLL_DIV • PLL lock count ( ) register setting: 0x0200 PLL_LOCKCNT •...
Page 373: Full-On Mode To Active Mode And Back
Dynamic Power Management Full-on Mode to Active Mode and Back Listing 8-1 Listing 8-2 provide code for transitioning from the full-on operating mode to active mode in C and Blackfin assembly code, respectively. Listing 8-1. Transitioning from Full-on Mode to Active Mode (C) void active(void) ADI_SYSCTRL_VALUES active;...
Page 374: Transition To Sleep Mode Or Deep Sleep Mode
Programming Examples R0 = w[FP+-sizeof(ADI_SYSCTRL_VALUES)+offse- tof(ADI_SYSCTRL_VALUES,uwPllCtl)]; bitset(R0,bitpos(BYPASS)); bitset(R0,bitpos(PLL_OFF)); /* optional */ w[FP+-sizeof(ADI_SYSCTRL_VALUES)+offse- tof(ADI_SYSCTRL_VALUES,uwPllCtl)] = R0; R0 = (SYSCTRL_WRITE | SYSCTRL_EXTVOLTAGE | SYSCTRL_PLLCTL); R1 = FP; R1 += -sizeof(ADI_SYSCTRL_VALUES); R2 = 0 (z); IMM32(P4,BFROM_SYSCONTROL); call(P4); SP += 12; (R7:0,P5:0) = [SP++]; unlink;...
Page 375 Dynamic Power Management Listing 8-3. Transitioning to Sleep Mode or Deep Sleep Mode (C) void sleep(void) ADI_SYSCTRL_VALUES sleep; bfrom_SysControl(SYSCTRL_EXTVOLTAGE | SYSCTRL_PLLCTL | SYSCTRL_READ, &sleep, NULL); sleep.uwPllCtl |= STOPCK; /* either: Sleep Mode */ sleep.uwPllCtl |= PDWN; /* or: Deep Sleep Mode */ bfrom_SysControl(SYSCTRL_WRITE | SYSCTRL_EXTVOLTAGE | SYSCTRL_PLLCTL, &sleep, NULL);...
Page 376: Set Wakeup Events And Enter Hibernate State
Programming Examples w[FP+-sizeof(ADI_SYSCTRL_VALUES)+offse- tof(ADI_SYSCTRL_VALUES,uwPllCtl)] = R0; R0 = (SYSCTRL_WRITE | SYSCTRL_EXTVOLTAGE | SYSCTRL_PLLCTL); R1 = FP; R1 += -sizeof(ADI_SYSCTRL_VALUES); R2 = 0 (z); IMM32(P4,BFROM_SYSCONTROL); call(P4); SP += 12; (R7:0,P5:0) = [SP++]; unlink; rts; __sleep.end: Set Wakeup Events and Enter Hibernate State Listing 8-5 Listing 8-6 provide code for configuring the regulator...
Page 377 Dynamic Power Management bfrom_SysControl(SYSCTRL_WRITE | SYSCTRL_VRCTL | SYSCTRL_EXTVOLTAGE, &hibernate, NULL); /* Hibernate State: no code executes until wakeup triggers reset */ Listing 8-6. Configuring Regulator Wakeups and Entering Hibernate State (ASM) __hibernate: link sizeof(ADI_SYSCTRL_VALUES)+2; [--SP] = (R7:0,P5:0); SP += -12; cli R6;...
Page 378: Perform A System Reset Or Soft-Reset
Programming Examples Perform a System Reset or Soft-Reset Listing 8-7 Listing 8-8 provide code for executing a system reset or a soft-reset (system and core reset) in C and Blackfin assembly code, respectively. Listing 8-7. Execute a System Reset or a Soft-Reset (C) void reset(void) bfrom_SysControl(SYSCTRL_SYSRESET, NULL, NULL);...
Page 379: In Full-On Mode, Change Vco Frequency, Core Clock Frequency, And System Clock Frequency
Dynamic Power Management __reset.end: In Full-on Mode, Change VCO Frequency, Core Clock Frequency, and System Clock Frequency Listing 8-9 Listing 8-10 provide C and Blackfin assembly code for changing the to VCO multiplier (from 10x to 21x), keeping the CLKIN divider at 1, and changing the divider (from 5 to 4) in the CSEL...
Page 380 Programming Examples Listing 8-10. Transition of Frequencies (ASM) __frequency: link sizeof(ADI_SYSCTRL_VALUES)+2; [--SP] = (R7:0,P5:0); SP += -12; /* write the struct */ R0 = 0; R0.L = SET_MSEL(21) ; /* Set MSEL = 5-63 --> VCO = CLKIN*MSEL */ w[FP+-sizeof(ADI_SYSCTRL_VALUES)+ offsetof(ADI_SYSCTRL_VALUES,uwPllCtl)] = R0;...
Page 381: Changing Voltage Levels
Dynamic Power Management /* call of SysControl function */ IMM32(P4,BFROM_SYSCONTROL); call (P4); /* R0 contains the result from SysControl */ SP += 12; (R7:0,P5:0) = [SP++]; unlink; rts; __frequency.end: Changing Voltage Levels Listing 8-11 provides C code for changing the voltage level dynamically. The User must include his own code for accessing the external voltage regulator.
Page 382 Programming Examples /* A delay loop is required to ensure VDDint is stable and the PLL has re-locked. As this is depending on the external voltage regulator circuitry the user must ensure timings are kept. The compiler (no optimization enabled) will create a loop that takes about 10 cycles.
Page 383: General-Purpose Ports
9 GENERAL-PURPOSE PORTS This chapter describes the general-purpose ports. Following an overview and a list of key features is a block diagram of the interface and a descrip- tion of operation. The chapter concludes with a programming model, consolidated register definitions, and programming examples. Overview The ADSP-BF50x Blackfin processors feature a rich set of peripherals, which, through a powerful pin multiplexing scheme, provides great flexi-...
Page 384 Features • PWM0 signals • GP Timer signals • Additional SPI0 and SPI1 slave selects • GPIOs Port G provides 16 pins: • SPORT1 signals • CAN signals • ACM signals • PPI signals • GP Timer signals • PWM1 signals •...
Page 385: Interface Overview
General-Purpose Ports • GP Timer signals • GPIOs Additionally, the TWI signals are provided on separate pins, independent of the ports. Interface Overview By default, all port F, port G, and port H pins are in general-purpose I/O (GPIO) mode. In this mode, a pin can function as a digital input, digital output, or interrupt input.
Page 386 Interface Overview Port F consists of 16 pins, referred to as , as shown in PF15 Table 9-1. All the input signals in the “Additional Use” column are enabled by their module only, regardless of the state of the PORTx_MUX registers.
Page 387: Port G Structure
General-Purpose Ports Port G Structure Table 9-2 shows the multiplexer scheme for port G. Port G is controlled by the registers. PORTG_MUX PORTG_FER Port G consists of 16 pins, referred to as , as shown in PG15 Table 9-2. Any GPIO can be enabled individually and overrides the peripheral func- tion if the respective bit in the register is cleared.
Page 388: Port H Structure
Interface Overview Port H Structure Table 9-3 shows the multiplexer scheme for port H. Port H is controlled by the registers. PORTH_MUX PORTH_FER Port H consists of 3 pins. (shown in Table 9-3) are GPIO capa- ble and operate in the same fashion as the Port F and Port G pins. Any GPIO can be enabled individually and overrides the peripheral func- tion if the respective bit in the register is cleared.
Page 389 General-Purpose Ports on other pins, depending on which pin function is selected. The input taps will see different signals than at the pins in the following cases: • All GPIO inputs except , and PG11 when GPIO is tapped with the respective set to 1.
Page 390: Pwm Unit Considerations
Interface Overview PWM Unit Considerations signal appears twice within Port F: on . If PWM0_SYNC PF12 both are configured as and selected, inputs will only be enabled PWM0_SYNC signal appears twice within Port F: on . If PWM0_TRIP PF11 both are configured as and selected, inputs will only be enabled PWM0_TRIP is not selected on either...
Page 391: Gp Counter Considerations
General-Purpose Ports • Pull up for will be enabled only if RSI is selected on SD_DATA[2] (that is, ) and the bit is set in PORTG_MUX[9:8] b#01 PU_Dat register. RSI_CONFIG • Pull up for will be enabled only if SD_DATA[7:4] SD_DATA[7:4] selected on (that is,...
Page 392: Gp Timer Interaction With Other Blocks
Interface Overview The function enable registers ( ) enable PORTF_FER PORTG_FER PORTH_FER the peripheral functionality for each individual pin of a port. GP Timer Interaction With Other Blocks inputs of the GP Timers connect to several differ- TACLKx TACIx ent subsystems of the ADSP-BF50x processor. Following are the details of these connections.
Page 393: Sport
General-Purpose Ports UART1 signals that appear in multiple ports, if selected on both, will have inputs and outputs enabled only on SPORT is configured as an output and TMR5 PORTF_MUX[3:2] b#10 SPORT0’s input enable is active, then is the clock input for RSCLK0 TMR5 RSCLK0...
Page 394: Performance/Throughput
Description of Operation Performance/Throughput , and pins are synchronized to the system clock ( SCLK When configured as outputs, the GPIOs can transition once every system clock cycle. When configured as inputs, the overall system design should take into account the potential latency between the core and system clocks. Changes in the state of port pins have a latency of 3 cycles before being detect- SCLK...
Page 395: General-Purpose I/O Modules
General-Purpose Ports  By default all peripheral pins are configured as inputs after reset. port F, port G, and port H pins are in GPIO mode. However, GPIO input drivers are disabled to minimize power consumption and any need of external pulling resistors. When the control bit in the function enable registers ( ) is set, PORTx_FER...
Page 396 Description of Operation  Note when using the GPIO as an input, the corresponding bit should also be set in the GPIO input enable register. Otherwise, changes at the input pins will not be recognized by the processor. The GPIO input enable registers ( , and PORTFIO_INEN PORTGIO_INEN...
Page 397 General-Purpose Ports  For GPIOs configured as edge-sensitive, a readback of 1 from one of these registers is sticky. That is, once it is set it remains set until cleared by user code. For level-sensitive GPIOs, the pin state is checked every cycle, so the readback value will change when the original level on the pin changes.
Page 398: Gpio Interrupt Processing
Description of Operation  If an edge-sensitive pin generates an interrupt request, the service routine must acknowledge the request by clearing the respective GPIO latch. This is usually performed through the clear registers. Read operations from the GPIO clear registers return the content of the GPIO data registers.
Page 399 General-Purpose Ports Then, an interrupt request can be generated according to the state of the pin (either high or low), an edge transition (low to high or high to low), or on both edge transitions (low to high and high to low). Input sensitivity is defined on a per-bit basis by the GPIO polarity registers ( PORTFIO_POLAR , and...
Page 400 Description of Operation When the GPIO’s input drivers are enabled while the GPIO direction reg- isters configure it as an output, software can trigger a GPIO interrupt by writing to the data/set/toggle registers. The interrupt service routine should clear the GPIO to acknowledge the request. Each of the three GPIO modules provides two independent interrupt channels.
Page 401 General-Purpose Ports START IS THE GPIO ENABLED IN PORTxIO_MASKA_D? (INPUT) IS THE GPIO SET IS THE INPUT AS AN OUTPUT IN DRIVER ENABLED IN PORTxIO_DIR? PORTxIO_INEN? (OUTPUT) IS THE GPIO EDGE-SENSITIVE (LEVEL SENSITIVE) (EDGE SENSITIVE) IS THE GPIO AS DEFINED IN SET TO ONE? PORTxIO_EDGE? IS EDGE...
Page 402 Description of Operation The GPIO mask interrupt set registers ( PORTxIO_MASKA_SET ) provide an alternative port to manipulate the GPIO PORTxIO_MASKB_SET mask interrupt registers. While a direct write to a mask interrupt register alters all bits in the register, writes to a mask interrupt set register can be used to set a single or a few bits only.
Page 403 General-Purpose Ports Figure 9-1 illustrates the interrupt flow of any GPIO module’s interrupt A channel. The interrupt B channel behaves identically. All GPIOs assigned to the same interrupt channel are OR’ed. (See Figure 9-2.) If multiple GPIOs are assigned to the same interrupt channel, it is up to the interrupt service routine to evaluate the GPIO data registers to determine the signaling interrupt source.
Page 404: Programming Model
Programming Model Programming Model Figure 9-3 Figure 9-4 show the programming model for the gen- eral-purpose ports. PERIPHERAL GPIO OR WRITE PORTx_MUX, WRITE PORTx_FER PERIPHERAL? TO SET APPROPRIATE PERIPHERAL BITS GPIO SEE PERIPHERAL FOR MORE DETAILS WRITE PORTx_FER TO CLEAR APPROPRIATE PFx, PGx, AND PHx BITS OUTPUT GPIO OUTPUT...
Page 405 General-Purpose Ports EDGE WRITE PORTxIO_EDGE TO SET EDGE OR LEVEL APPROPRIATE BITS FOR EDGE SENSITIVITY SENSITIVE? LEVEL EDGE RISING/ WRITE PORTxIO_EDGE TO CLEAR RISING OR FALLING FALLING OR BOTH? APPROPRIATE BITS FOR LEVEL SENSITIVITY BOTH WRITE PORTxIO_BOTH TO SET HIGH LEVEL HIGH APPROPRIATE BITS FOR BOTH EDGE SENSITIVITY OR LOW?
Page 406: Hysteresis Control
Hysteresis Control Hysteresis Control The ADSP-BF50x contains additional registers controlling the hysteresis (via Schmitt triggering) for Port F, Port G, and Port H. These are also included for pins other than GPIOs. Figure 9-5 Figure 9-7 show the bit descriptions of these registers. PORTx Hysteresis (PORTx_HYSTERESIS) Register This register configures Schmitt triggering (SE) for the PORTx inputs.
Page 407 General-Purpose Ports Port G Hysteresis Register (PORTG_HYSTERESIS) 15 14 13 12 11 10 Reset = 0x5555 PG15to14_SE PG0_SE PG13o12_SE PG1_SE PG11to9_SE PG2_SE PG8to6_SE PG5to3_SE Figure 9-6. Port G Hysteresis Register Port H Hysteresis Register (PORTH_HYSTERESIS) 15 14 13 12 11 10 Reset = 0x0015 Reserved PH0_SE...
Page 408: Drive Strength Control
Drive Strength Control register sets the Schmitt trigger (SE) for various NONGPIO_HYSTERESIS ADSP-BF50x signals. Non-GPIO Hysteresis Register (NONGPIO_HYSTERESIS) 15 14 13 12 11 10 Reset = 0x0015 Reserved ARDY_SE 00 - Enable hysteresis for JTAG_SE 00 - Disable hysteresis for ARDY pin input from Flash 01 - Disable hysteresis for JTAG input signals...
Page 409: Memory-Mapped Gpio Registers
General-Purpose Ports Memory-Mapped GPIO Registers The GPIO registers are part of the system memory-mapped registers (MMRs). Figure 9-10 through Figure 9-30 on page 9-41 illustrate the GPIO registers. The addresses of the programmable flag MMRs appear in Appendix B.  Figure 9-10 through Figure...
Page 410 Memory-Mapped GPIO Registers Figure 9-11 shows the Port G Multiplexer Control register. Refer to Table 9-2 on page 9-5 for more information on multiplexed configura- tions within Port G. Port G Multiplexer Control Register (PORTG_MUX) 15 14 13 12 11 10 Reset = 0x0000 PG15to14_MUX PG0_MUX...
Page 411 General-Purpose Ports Figure 9-12 shows the Port H Multiplexer Control register. Refer to Table 9-3 on page 9-6 for more information on multiplexed configura- tions within Port H. Port H Multiplexer Control Register (PORTH_MUX) 15 14 13 12 11 10 Reset = 0x0000 Reserved PH0_MUX...
Page 412: Function Enable Registers (Portx_Fer)
Memory-Mapped GPIO Registers Function Enable Registers (PORTx_FER) Function Enable Registers (PORTx_FER) For all bits, 0 - GPIO mode, 1 - Enable peripheral function 15 14 13 12 11 10 Reset = 0x0000 Px15 Px14 Px13 Px12 Px11 Px10 Figure 9-13. Function Enable Registers GPIO Direction Registers (PORTxIO_DIR) GPIO Direction Registers (PORTxIO_DIR) For all bits, 0 - Input, 1 - Output...
Page 413: Gpio Input Enable Registers (Portxio_Inen)
General-Purpose Ports GPIO Input Enable Registers (PORTxIO_INEN) GPIO Input Enable Registers (PORTxIO_INEN) For all bits, 0 - Input Buffer Disabled, 1 - Input Buffer Enabled 15 14 13 12 11 10 Reset = 0x0000 Px0 Input Enable Px1 Input Enable Px2 Input Enable Px3 Input Enable Px15 Input Enable...
Page 414: Gpio Set Registers (Portxio_Set)
Memory-Mapped GPIO Registers GPIO Set Registers (PORTxIO_SET) GPIO Set Registers (PORTxIO_SET) Write-1-to-set 15 14 13 12 11 10 Reset = 0x0000 Set Px0 Set Px1 Set Px2 Set Px3 Set Px15 Set Px4 Set Px14 Set Px5 Set Px13 Set Px6 Set Px12 Set Px7 Set Px11...
Page 415: Gpio Toggle Registers (Portxio_Toggle)
General-Purpose Ports GPIO Toggle Registers (PORTxIO_TOGGLE) GPIO Toggle Registers (PORTxIO_TOGGLE) Write-1-to-toggle 15 14 13 12 11 10 Reset = 0x0000 Toggle Px0 Toggle Px1 Toggle Px2 Toggle Px3 Toggle Px15 Toggle Px4 Toggle Px14 Toggle Px5 Toggle Px13 Toggle Px6 Toggle Px12 Toggle Px7 Toggle Px11...
Page 416: Interrupt Sensitivity Registers (Portxio_Edge)
Memory-Mapped GPIO Registers Interrupt Sensitivity Registers (PORTxIO_EDGE) Interrupt Sensitivity Registers (PORTxIO_EDGE) For all bits, 0 - Level, 1 - Edge 15 14 13 12 11 10 Reset = 0x0000 Px0 Sensitivity Px1 Sensitivity Px2 Sensitivity Px3 Sensitivity Px15 Sensitivity Px4 Sensitivity Px14 Sensitivity Px5 Sensitivity Px13 Sensitivity...
Page 417: Gpio Mask Interrupt Registers (Portxio_Maska/B)
General-Purpose Ports GPIO Mask Interrupt Registers (PORTxIO_MASKA/B) GPIO Mask Interrupt A Registers (PORTxIO_MASKA) For all bits, 1 - Enable, 0 - Disable 15 14 13 12 11 10 Reset = 0x0000 Enable Px0 Interrupt A Enable Px1 Interrupt A Enable Px2 Interrupt A Enable Px3 Interrupt A Enable Px15 Interrupt Enable Px4 Interrupt A...
Page 418: Gpio Mask Interrupt Set Registers (Portxio_Maska/B_Set)
Memory-Mapped GPIO Registers GPIO Mask Interrupt Set Registers (PORTxIO_MASKA/B_SET) GPIO Mask Interrupt A Set Registers (PORTxIO_MASKA_SET) For all bits, 1 - Set 15 14 13 12 11 10 Reset = 0x0000 Set Px0 Interrupt A Enable Set Px1 Interrupt A Enable Set Px2 Interrupt A Set Px15 Interrupt A...
Page 419 General-Purpose Ports GPIO Mask Interrupt B Set Registers (PORTxIO_MASKB_SET) For all bits, 1 - Set 15 14 13 12 11 10 Reset = 0x0000 Set Px0 Interrupt B Enable Set Px1 Interrupt B Enable Set Px2 Interrupt B Set Px15 Interrupt B Enable Enable Set Px3 Interrupt B...
Page 420: Gpio Mask Interrupt Clear Registers (Portxio_Maska/B_Clear)
Memory-Mapped GPIO Registers GPIO Mask Interrupt Clear Registers (PORTxIO_MASKA/B_CLEAR) GPIO Mask Interrupt A Clear Registers (PORTxIO_MASKA_CLEAR) For all bits, 1 - Clear 15 14 13 12 11 10 Reset = 0x0000 Clear Px0 Interrupt A Enable Clear Px1 Interrupt A Enable Clear Px2 Interrupt A Clear Px15 Interrupt A...
Page 421 General-Purpose Ports GPIO Mask Interrupt B Clear Registers (PORTxIO_MASKB_CLEAR) For all bits, 1 - Clear 15 14 13 12 11 10 Reset = 0x0000 Clear Px0 Interrupt B Enable Clear Px1 Interrupt B Enable Clear Px2 Interrupt B Clear Px15 Interrupt B Enable Enable Clear Px3 Interrupt B...
Page 422: Gpio Mask Interrupt Toggle Registers (Portxio_Maska/B_Toggle)
Memory-Mapped GPIO Registers GPIO Mask Interrupt Toggle Registers (PORTxIO_MASKA/B_TOGGLE) GPIO Mask Interrupt A Toggle Registers (PORTxIO_MASKA_TOGGLE) For all bits, 1 - Toggle 15 14 13 12 11 10 Reset = 0x0000 Toggle Px0 Interrupt A Enable Toggle Px1 Interrupt A Toggle Px15 Enable Interrupt A Enable...
Page 423: Programming Examples
General-Purpose Ports GPIO Mask Interrupt B Toggle Registers (PORTxIO_MASKB_TOGGLE) For all bits, 1 - Toggle 15 14 13 12 11 10 Reset = 0x0000 Toggle Px0 Interrupt B Enable Toggle Px1 Interrupt B Enable Toggle Px15 Interrupt B Enable Toggle Px2 Interrupt B Toggle Px14 Enable Interrupt B Enable...
Page 424 Programming Examples w[p0] = r0; /* set port f direction register to enable some GPIO as output, remaining are input */ p0.l = lo(PORTFIO_DIR); p0.h = hi(PORTFIO_DIR); r0.h = 0x0000; r0.l = 0x0FC0; w[p0] = r0; ssync; /* set port f clear register */ p0.l = lo(PORTFIO_CLEAR);...
Page 425: 10 General-Purpose Timers
Specific Information for the ADSP-BF50x For details regarding the number of GP timers for the ADSP-BF50x prod- uct, refer to ADSP-BF504, ADSP-BF504F, ADSP-BF506F Embedded Processor Data Sheet. For GP Timer interrupt vector assignments, refer to Table 4-3 on page 4-19 Chapter 4, “System...
Page 426: Overview
Overview Overview The general-purpose timers support the following operating modes: • Single-shot mode for interval timing and single pulse generation • Pulse width modulation (PWM) generation with consistent update of period and pulse width values • External signal capture mode with consistent update of period and pulse width values •...
Page 427: External Interface
General-Purpose Timers TIMER 0 TIMER0_CONFIG LEADING EDGE TIMER0_PERIOD (WRITE) TIMEN0 ENABLE LATCH TIMDIS0 TIMER0_PERIOD (READ) PERIOD TRUN0 MATCH COMPARATOR TOVF_ERR0 INTERRUPT SCLK CONTROL TMRCLK TIMIL0 TIMER0_COUNTER OVERFLOW TACLK0 TMR0 WIDTH MATCH COMPARATOR TMR0 CONTROL TIMER0_WIDTH (READ) EDGE DETECTOR TACI0 TIMER0_WIDTH (WRITE) TRAILING EDGE Figure 10-1.
Page 428: Internal Interface
Description of Operation Clock and capture input pins are sampled every cycle. The duration SCLK of every low or high state must be at least one . Therefore, the maxi- SCLK mum allowed frequency of timer input signals is SCLK Internal Interface Timer registers are always accessed by the core through the 16-bit PAB bus.
Page 429: Interrupt Processing
General-Purpose Timers is 32-bits wide. A single atomic 32-bit read can report the status of all cor- responding timers. Before a timer can be enabled, its mode of operation is programmed in the individual timer-specific register. Then, the timers are TIMER_CONFIG started by writing a “1”...
Page 430 Description of Operation Figure 10-2 shows the interrupt structure of the timers. ILLEGAL COUNT = WIDTH TIMER_WIDTH COUNT = PERIOD ILLEGAL TIMER _PERIOD TRAILING EDGE COUNTER LEADING OVERFLOW EDGE PERIOD_CNT PWM_OUT WDTH_CAP EXT_CLK PWM_OUT WDTH_CAP EXT_CLK TMODE TMODE INTERRUPT ERROR EVENT EVENT IRQ_ENA PWM_OUT...
Page 431: Illegal States
General-Purpose Timers without interrupt generation, set but leave the interrupt masked IRQ_ENA at the system level. If enabled by , interrupt requests are also gen- IRQ_ENA erated by error conditions as reported by the bits. TOVF_ERR The system interrupt controller enables flexible interrupt handling. All timers may or may not share the same CEC interrupt channel, so that a single interrupt routine services more than one timer.
Page 432 Description of Operation • Overflow. The timer counter was incremented instead of doing a rollover when it was holding the maximum possible count value of 0xFFFF FFFF. The counter does not have a large enough range to express the next greater value and so erroneously loads a new value of 0x0000 0000.
Page 433 General-Purpose Timers Table 10-1. Overview of Illegal States PWM_OUT, Startup == 0 Anything b#10 PERIOD_CNT = (No boundary condition == 1 Anything b#10 tests performed on  2 TIMER_WIDTH) Anything change change Rollover == 0 Anything b#10 == 1 Anything b#11 ...
Page 434: Modes Of Operation
Modes of Operation Table 10-1. Overview of Illegal States (Cont’d) WDTH_CAP Startup TIMER_PERIOD and TIMER_WIDTH are read-only in this mode, no error possible. Rollover TIMER_PERIOD and TIMER_WIDTH are read-only in this mode, no error possible. Overflow Anything Anything b#01 EXT_CLK Startup == 0 Anything...
Page 435 General-Purpose Timers Setting the field to in the register enables TMODE b#01 TIMER_CONFIG mode. Here, the pin is an output, but it can be disabled by PWM_OUT setting the bit in the register. OUT_DIS TIMER_CONFIG mode, the bits PWM_OUT PULSE_HI PERIOD_CNT IRQ_ENA OUT_DIS...
Page 436: Output Pad Disable
Modes of Operation Once a timer has been enabled, the timer counter register is loaded with a starting value. If = 0, the timer counter starts at 0x1. If CLK_SEL = 1, it is reset to 0x0 as in mode. The timer counts CLK_SEL EXT_CLK upward to the value of the timer period register.
Page 437: Single Pulse Generation
General-Purpose Timers Single Pulse Generation If the bit is cleared, the mode generates a single pulse PERIOD_CNT PWM_OUT on the pin. This mode can also be used to implement a precise delay. The pulse width is defined by the register, and the TIMER_WIDTH register is not used.
Page 438: Pulse Width Modulation Waveform Generation
Modes of Operation Pulse Width Modulation Waveform Generation If the bit is set, the internally clocked timer generates rectan- PERIOD_CNT gular signals with well-defined period and duty cycle (PWM patterns). This mode also generates periodic interrupts for real-time signal processing. The 32-bit registers are programmed with TIMER_PERIOD...
Page 439 General-Purpose Timers Figure 10-5 shows timing details. EXAMPLE TIMER ENABLE TIMING (PWM_OUT MODE, PERIOD_CNT = 1) SCLK TIMER_PERIOD TIMER_WIDTH TIMER_COUNTER TIMEN TRUN TMR pin, PULSE_HI = 0 TMR pin, PULSE_HI = 1 W1S TO TIMER_ENABLE Figure 10-5. Timer Enable Timing If enabled, a timer interrupt is generated at the end of each period.
Page 440: Pulse_Hi Toggle Mode
Modes of Operation Although the hardware reports an error if the value equals TIMER_WIDTH value, this is still a valid operation to implement PWM TIMER_PERIOD patterns with 100% duty cycle. If doing so, software must generally ignore flags. Pulse width values greater than the period value are TOVL_ERR not recommended.
Page 441 General-Purpose Timers PERIOD 1 TOGGLE_HI = 0 PULSE_HI = 1 TMR0 ACTIVE HIGH TOGGLE_HI = 0 PULSE_HI = 1 TMR1 ACTIVE HIGH TOGGLE_HI = 0 PULSE_HI = 1 TMR2 ACTIVE HIGH TIMER ENABLE Figure 10-6. Example of Timers With Pulses Aligned to Asserting Edge mode enables control of the timing of both the asserting TOGGLE_HI and deasserting edges of the output waveform produced.
Page 442 Modes of Operation Figure 10-7 shows an example with three timers running with the same period settings. When software does not alter the PWM settings at run-time, the duty cycle is 50%. The values of the registers TIMER_WIDTH control the phase between the signals. WAVEFORM WAVEFORM PERIOD 1...
Page 443 General-Purpose Timers WAVEFORM WAVEFORM PERIOD 1 PERIOD 2 TIMER TIMER TIMER TIMER PERIOD 1 PERIOD 2 PERIOD 3 PERIOD 4 TOGGLE_HI = 1 TMR0 PULSE_HI = 0 ACTIVE ACTIVE ACTIVE ACTIVE HIGH HIGH TOGGLE_HI = 1 TMR1 PULSE_HI = 1 ACTIVE ACTIVE ACTIVE...
Page 444 Modes of Operation per1 = period/2 ; wid1 = width/2 ; per2 = period/2 ; wid2 = width/2 ; waitfor (interrupt) ; write (TIMER_PERIOD, per1) ; write (TIMER_WIDTH, per1 - wid1) ; waitfor (interrupt) ; write (TIMER_PERIOD, per2) ; write (TIMER_WIDTH, wid2) ; As shown in this example, the pulses produced do not need to be symmet- ric ( does not need to equal...
Page 445: Externally Clocked Pwm_Out
General-Purpose Timers Externally Clocked PWM_OUT By default, the timer is clocked internally by . Alternatively, if the SCLK bit in the register is set, the timer is clocked by CLK_SEL TIMER_CONFIG . The is normally input from the pin, but may be PWM_CLK PWM_CLK TACLK...
Page 446: Stopping The Timer In Pwm_Out Mode
Modes of Operation with the PPI, refer to “Frame Synchronization in GP Modes” in Chapter 20, Parallel Peripheral Interface. Stopping the Timer in PWM_OUT Mode In all mode variants, the timer treats a disable operation (W1C to PWM_OUT ) as a “stop is pending” condition. When disabled, it auto- TIMER_DISABLE matically completes the current waveform and then stops cleanly.
Page 447 General-Purpose Timers run as if nothing happened. Typically, software should disable a PWM_OUT timer and then wait for it to stop itself. Figure 10-9 shows detailed timing. EXAMPLE TIMER DISABLE TIMING (PWM_OUT MODE, PERIOD_CNT = 1) SCLK TIMER_PERIOD TIMER_WIDTH TIMER_COUNTER TIMEN TRUN TMR PIN, PULSE_HI = 0...
Page 448: Pulse Width Count And Capture (Wdth_Cap) Mode
Modes of Operation Pulse Width Count and Capture (WDTH_CAP) Mode Use the WDTH_CAP mode, often simply called “capture mode,” to mea- sure pulse widths on the TMR or TACI input pins, or to “receive” PWM signals. Figure 10-10 shows a flow diagram for WDTH_CAP mode. DATA BUS TIMER_PERIOD TIMER_WIDTH...
Page 449 General-Purpose Timers When enabled in this mode, the timer resets the count in the register to 0x0000 0001 and does not start counting until TIMER_COUNTER it detects a leading edge on the pin. When the timer detects the first leading edge, it starts incrementing. When it detects a trailing edge of a waveform, the timer captures the cur- rent 32-bit value of the register into the width buffer.
Page 450 Modes of Operation The current timer counter value is always copied to the width buffer and period buffer registers at the trailing and leading edges of the input signal, respectively, but these values are not visible to software. A measurement report event samples the captured values into visible registers and sets the timer interrupt to signal that are ready to...
Page 451 General-Purpose Timers SCLK TMR PIN, PULSE_HI = 0 TMR PIN, PULSE_HI = 1 TIMER_COUNTER TIMER_PERIOD BUFFER TIMER_WIDTH BUFFER TIMER_PERIOD TIMER_WIDTH TIMIL TOVF_ERR TIMEN STARTS MEASUREMENT MEASUREMENT COUNTING REPORT REPORT NOTE: FOR SIMPLICITY, THE SYNCHRONIZATION DELAY BETWEEN TMR PIN EDGES AND BUFFER REGISTER UPDATES IS NOT SHOWN. Figure 10-11.
Page 452 Modes of Operation SCLK TMR PIN, PULSE_HI = 0 TMR PIN, PULSE_HI = 1 TIMER_COUNTER TIMER_PERIOD BUFFER TIMER_WIDTH BUFFER TIMER_PERIOD TIMER_WIDTH TIMIL TOVF_ERR TIMEN STARTS MEASUREMENT MEASUREMENT MEASUREMENT COUNTING REPORT REPORT REPORT NOTE: FOR SIMPLICITY, THE SYNCHRONIZATION DELAY BETWEEN TMR PIN EDGES AND BUFFER REGISTER UPDATES IS NOT SHOWN.
Page 453 General-Purpose Timers  When using the = 0 mode described above to measure PERIOD_CNT the width of a single pulse, it is recommended to disable the timer after taking the interrupt that ends the measurement interval. If desired, the timer can then be reenabled as appropriate in preparation for another measurement.
Page 454 Modes of Operation SCLK TMR PIN, PULSE_HI = 0 TMR PIN, PULSE_HI = 1 0xFFFF 0xFFFF 0xFFFF 0xFFFF TIMER_COUNTER FFFC FFFD FFFE FFFF TIMER_PERIOD BUFFER TIMER_WIDTH BUFFER TIMER_PERIOD TIMER_WIDTH TIMIL TOVF_ERR TIMEN STARTS ERROR MEASUREMENT COUNTING REPORT REPORT NOTE: FOR SIMPLICITY, THE SYNCHRONIZATION DELAY BETWEEN TMR PIN EDGES AND BUFFER REGISTER UPDATES IS NOT SHOWN.
Page 455 General-Purpose Timers SCLK TMR pin, PULSE_HI = 0 TMR pin, PULSE_HI = 1 0xFFFF 0xFFFF 0xFFFF 0xFFFF TIMER_COUNTER FFFC FFFD FFFE FFFF TIMER_PERIOD BUFFER TIMER_WIDTH BUFFER TIMER_PERIOD TIMER_WIDTH TIMIL TOVF_ERR TIMEN STARTS MEASUREMENT ERROR COUNTING REPORT REPORT NOTE: FOR SIMPLICITY, THE SYNCHRONIZATION DELAY BETWEEN TMR PIN EDGES AND BUFFER REGISTER UPDATES IS NOT SHOWN.
Page 456: Autobaud Mode
Modes of Operation Both are sticky bits, and software must explicitly clear TIMIL TOVF_ERR them. If the timer overflowed and = 1, neither the PERIOD_CNT nor the register were updated. If the timer TIMER_PERIOD TIMER_WIDTH overflowed and = 0, the regis- PERIOD_CNT TIMER_PERIOD...
Page 457: External Event (Ext_Clk) Mode
General-Purpose Timers External Event (EXT_CLK) Mode Use the EXT_CLK mode (sometimes referred to as the counter mode) to count external events—that is, signal edges on the TMR pin (which is an input in this mode). Figure 10-15 shows a flow diagram for EXT_CLK mode.
Page 458: Programming Model
Programming Model DATA BUS TIMER_PERIOD RESET CLOCK TIMER_COUNTER LEADING PULSE_HI EDGE TMR pin EQUAL? DETECT INTERRUPT TIMER_ENABLE Figure 10-15. Timer Flow Diagram, Mode EXT_CLK Programming Model The architecture of the timer block enables any of the timers within this block to work individually or synchronously along with others as a group of timers.
Page 459: Timer Registers
General-Purpose Timers If in mode the PWM patterns of the second period differ from PWM_OUT the patterns of the first one, the initialization sequence above might become: 1. Set timer mode to PWM_OUT 2. Write first value pair. TIMER_WIDTH TIMER_PERIOD 3.
Page 460: Timer Enable Register (Timer_Enable)
Timer Registers Additionally, three registers are shared between the timers within a block: • – timer enable register TIMER_ENABLE[15:0] • – timer disable register TIMER_DISABLE[15:0] • – timer status register TIMER_STATUS[31:0] The size of accesses is enforced. A 32-bit access to a register TIMER_CONFIG or a 16-bit access to a...
Page 461: Timer Disable Register (Timer_Disable)
General-Purpose Timers Timer Enable Register (TIMER_ENABLE) 15 14 13 12 11 10 Reset = 0x0000 TIMEN7 (Timer7 Enable) TIMEN0 (Timer0 Enable) 1 - Enable timer 1 - Enable timer Read as 1 when enabled Read as 1 when enabled TIMEN6 (Timer6 Enable) TIMEN1 (Timer1 Enable) 1 - Enable timer 1 - Enable timer...
Page 462 Timer Registers Timer Disable Register (TIMER_DISABLE) 15 14 13 12 11 10 Reset = 0x0000 TIMDIS7 (Timer7 Disable) TIMDIS0 (Timer0 Disable) 1 - Disable timer 1 - Disable timer Read as 1 if this timer is enabled Read as 1 if this timer is enabled TIMDIS6 (Timer6 Disable) TIMDIS1 (Timer1 Disable) 1 - Disable timer...
Page 463: Timer Status Register (Timer_Status)
General-Purpose Timers Timer Status Register (TIMER_STATUS) register indicates the status of the timers and is used to TIMER_STATUS check the status of multiple timers with a single read. Status bits are sticky and W1C. The bits can clear themselves, which they do when a TRUN mode timer stops at the end of a period.
Page 464 Timer Registers Timer Status Register (TIMER_STATUS) All bits are W1C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset = 0x0000 0000 TRUN7 (Timer7 Slave Enable Status) TIMIL4 (Timer4 Interrupt) Read as 1 if timer Indicates an interrupt request running, W1C to abort in when IRQ_ENA is set...
Page 465: Timer Configuration Register (Timer_Config)
General-Purpose Timers Timer Configuration Register (TIMER_CONFIG) The operating mode for each timer is specified by its regis- TIMER_CONFIG ter. The register, shown in Figure 10-19, may be written TIMER_CONFIG only when the timer is not running. After disabling the timer in PWM_OUT mode, make sure the timer has stopped running by checking its bit in...
Page 466: Timer Counter Register (Timer_Counter)
Timer Registers Timer Configuration Register (TIMER_CONFIG) 15 14 13 12 11 10 Reset = 0x0000 TMODE[1:0] (Timer Mode) 00 - Reset state - unused 01 - PWM_OUT mode 10 - WDTH_CAP mode 11 - EXT_CLK mode ERR_TYP[1:0] (Error PULSE_HI Type) - RO 0 - Negative action pulse 00 - No error 1 - Positive action pulse...
Page 467: Timer Period (Timer_Period) And Timer Width (Timer_Width) Registers
General-Purpose Timers While the processor core is being accessed by an external emulator debug- ger, all code execution stops. By default, the register also TIMER_COUNTER halts its counting during an emulation access in order to remain synchro- nized with the software. While stopped, the count does not advance—in mode, the pin waveform is “stretched”;...
Page 468 Timer Registers Usage of the register, shown in Figure 10-21, and the TIMER_PERIOD register, shown in Figure 10-22, varies depending on the TIMER_WIDTH mode of the timer: • In PWM_OUT mode, both the TIMER_PERIOD and TIMER_WIDTH register values can be updated “on-the-fly” since the values change simultaneously.
Page 469 General-Purpose Timers different setting for each of the first three timer periods after the timer is enabled, the procedure to follow is: 1. Program the first set of register values. 2. Enable the timer. 3. Immediately program the second set of register values. 4.
Page 470: Summary
Timer Registers Timer Width Register (TIMER_WIDTH) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset = 0x0000 0000 Timer Width[31:16] 15 14 13 12 11 10 Timer Width[15:0] Figure 10-22. Timer Width Register Summary Table 10-2 summarizes control bit and register usage in each timer mode.
Page 471 General-Purpose Timers Table 10-2. Control Bit and Register Usage Chart (Cont’d) Bit / Register PWM_OUT Mode WDTH_CAP Mode EXT_CLK Mode TIN_SEL Depends on CLK_SEL: 1 - Select TACI input Unused 0 - Select TMR pin If CLK_SEL = 1, input 1 - Count TMRCLK clocks 0 - Count TACLK...
Page 472 Timer Registers Table 10-2. Control Bit and Register Usage Chart (Cont’d) Bit / Register PWM_OUT Mode WDTH_CAP Mode EXT_CLK Mode Counter RO: Counts up on RO: Counts up on RO: Counts up on SCLK or PWM_CLK SCLK TMR pin event TRUN Read: Timer slave Read: Timer slave...
Page 473: Programming Examples
General-Purpose Timers Programming Examples Listing 10-1 configures the port control registers in a way that enables pins associated with Port G. This example assumes are connected TMR1-7 to Port G bits 5–11. Listing 10-1. Port Setup timer_port_setup: [--sp] = (r7:7, p5:5); p5.h = hi(PORTG_FER);...
Page 474 Programming Examples Listing 10-2. Signal Generation // #define SINGLE_PULSE timer45_signal_generation: [--sp] = (r7:7, p5:5); p5.h = hi(TIMER_ENABLE); p5.l = lo(TIMER_ENABLE); #ifdef SINGLE_PULSE r7.l = PULSE_HI | PWM_OUT; #else r7.l = PERIOD_CNT | PULSE_HI | PWM_OUT; #endif w[p5 + TIMER5_CONFIG - TIMER_ENABLE] = r7; w[p5 + TIMER4_CONFIG - TIMER_ENABLE] = r7;...
Page 475 General-Purpose Timers Listing 10-3. Interrupt Setup timer5_interrupt_setup: [--sp] = (r7:7, p5:5); p5.h = hi(IMASK); p5.l = lo(IMASK); /* register interrupt service routine */ r7.h = hi(isr_timer5); r7.l = lo(isr_timer5); [p5 + EVT12 - IMASK] = r7; /* unmask IVG12 in CEC */ r7 = [p5];...
Page 476 Programming Examples The example shown in Listing 10-4 does not drive the pin. It gener- ates periodic interrupt requests every 0x1000 SCLK cycles. If the preprocessor constant was defined, timer 5 requests an SINGLE_PULSE interrupt only once. Unlike in a real application, the purpose of the inter- rupt service routine shown in this example is just the clearing of the interrupt request and counting interrupt occurrences.
Page 477 General-Purpose Timers [--sp] = (r7:7, p5:5); p5.h = hi(TIMER_STATUS); p5.l = lo(TIMER_STATUS); r7.h = hi(TIMIL5); r7.l = lo(TIMIL5); [p5] = r7; r0+= 1; ssync; (r7:7, p5:5) = [sp++]; astat = [sp++]; rti; isr_timer5.end: Listing 10-5 illustrates how two timers can generate two non-overlapping clock pulses as typically required for break-before-make scenarios.
Page 478 Programming Examples ENABLE IRQ1 IRQ2 IRQ3 TMR5 TMR4 P/2 - W/2 P - W/2 Figure 10-23. Non-Overlapping Clock Pulses same times with the exception of the first timer 5 interrupt (at IRQ1 which is not visible to timer 4. Listing 10-5. Non-Overlapping Clock Pulses #define P 0x1000 /* signal period */ #define W 0x0600...
Page 479 General-Purpose Timers r0.h = hi(P); r1.l = lo(W); r1.h = hi(W); r2 = r1 >> 1; /* W/2 */ r3 = r0 >> 1; /* P/2 */ r4 = r3 - r2; /* P/2 - W/2 */ r5 = r0 - r2; /* P - W/2 */ /* write values for initial period */ [p5 + TIMER4_PERIOD - TIMER_ENABLE] = r0;...
Page 480 Programming Examples r7 = [p5 + TIMER5_PERIOD - TIMER_ENABLE]; r6 = [p5 + TIMER5_WIDTH - TIMER_ENABLE]; r5 = r7 - r6; [p5 + TIMER5_WIDTH - TIMER_ENABLE] = r5; r5 = [p5 + TIMER4_WIDTH - TIMER_ENABLE]; r7 = r7 - r5; CC = r7 <...
Page 481 General-Purpose Timers .section L1_code; timer5_capture: [--sp] = (r7:7, p5:5); /* setup DAG2 */ r7.h = hi(buffReceive); r7.l = lo(buffReceive); i2 = r7; b2 = r7; l2 = length(buffReceive)*4; /* config timer for high pulses capture */ p5.h = hi(TIMER_ENABLE); p5.l = lo(TIMER_ENABLE); r7.l = EMU_RUN|IRQ_ENA|PERIOD_CNT|PULSE_HI|WDTH_CAP;...
Page 482: Unique Information For The Adsp-Bf50X Processor
Unique Information for the ADSP-BF50x Processor astat = [sp++]; rti; isr_timer5.end: Unique Information for the ADSP-BF50x Processor The ADSP-BF50x processor features one general-purpose timer module that contains eight identical 32-bit timers. Each timer can be individually configured to operate in various modes. Although the timers operate com- pletely independently of each other, all of them can be started and stopped simultaneously for synchronous operation.
Page 483 General-Purpose Timers  If the PPI frame syncs are applied externally, timer 0 and timer 1 are still fully functional and can be used for other purposes not involving the pins. Timer 0 and timer 1 must not drive their TMRx pins.
Page 484 Unique Information for the ADSP-BF50x Processor 10-60 ADSP-BF50x Blackfin Processor Hardware Reference...
Page 485: 11 Core Timer
Specific Information for the ADSP-BF50x For details regarding the number of core timers for the ADSP-BF50x product, refer to ADSP-BF504, ADSP-BF504F, ADSP-BF506F Embedded Processor Data Sheet. For Core Timer interrupt vector assignments, refer to Table 4-3 on page 4-19 Chapter 4, “System...
Page 486: Timer Overview
Timer Overview inside the Blackfin core and runs at the core clock ( ) rate. Core timer CCLK features include: • 32-bit timer with 8-bit prescaler • Operates at core clock ( ) rate CCLK • Dedicated high-priority interrupt channel •...
Page 487: Internal Interfaces
Core Timer Internal Interfaces The core timer is accessed through the 32-bit register access bus (RAB). The module is clocked by the core clock . The timer’s dedicated inter- CCLK rupt request is a higher priority than requests from all other peripherals. Description of Operation The software should initialize the register before the timer is...
Page 488: Core Timer Registers
Core Timer Registers (SIC). Therefore, the interrupt processing is also completely in the CCLK domain.  The core timer interrupt request is edge-sensitive and cleared by hardware automatically as soon as the interrupt is serviced. bit in the register indicates that an interrupt has been gen- TINT TCNTL erated.
Page 489: Core Timer Control Register (Tcntl)
Core Timer Core Timer Control Register (TCNTL) register, shown in Figure 11-2, functions as control and status TCNTL register. Core Timer Control Register (TCNTL) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset = Undefined 15 14 13 12 11 10 TMPWR...
Page 490: Core Timer Period Register (Tperiod)
Core Timer Registers Writes to are ignored once the timer is running. TCOUNT Core Timer Count Register (TCOUNT) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset = Undefined Count Value[31:16] 15 14 13 12 11 10 Count Value[15:0] Figure 11-3.
Page 491: Core Timer Scale Register (Tscale)
Core Timer Core Timer Scale Register (TSCALE) The TSCALE register is shown in Figure 11-5. The register stores the scal- ing value that is one less than the number of cycles between decrements of TCOUNT. For example, if the value in the TSCALE register is 0, the counter register decrements once every CCLK clock cycle.
Page 492 Programming Examples r0.l = lo(isr_core_timer); r0.h = hi(isr_core_timer); [p1 + EVT6 - IMASK] = r0; r0 = [p1]; bitset(r0, bitpos(EVT_IVTMR)); [p1] = r0; /* Prescaler = 50, Period = 10,000,000, First Period = 20,000,000 p1.l = lo(TCNTL); p1.h = hi(TCNTL); r0 = 50 (z);...
Page 493: Unique Information For The Adsp-Bf50X Processor
Core Timer Unique Information for the ADSP-BF50x Processor None. ADSP-BF50x Blackfin Processor Hardware Reference 11-9...
Page 494 Unique Information for the ADSP-BF50x Processor 11-10 ADSP-BF50x Blackfin Processor Hardware Reference...
Page 495: 12 Watchdog Timer
Specific Information for the ADSP-BF50x For details regarding the number of watchdog timers for the ADSP-BF50x product, refer to ADSP-BF504, ADSP-BF504F, ADSP-BF506F Embedded Processor Data Sheet. For Watchdog Timer interrupt vector assignments, refer to Table 4-3 on page 4-19 Chapter 4, “System...
Page 496 Overview and Features Watchdog timer key features include: • 32-bit watchdog timer • 8-bit disable bit pattern • System reset on expire option • NMI on expire option • General-purpose interrupt option Typically, the watchdog timer is used to supervise stability of the system software.
Page 497: Interface Overview
Watchdog Timer Interface Overview Figure 12-1 provides a block diagram of the watchdog timer. WDEN WDOG_CNT WDOG_CTL WDRO WDEV RELOAD WRITE READ RESET WDOG_STAT SCLK EXPIRE EVENT CONTROL Figure 12-1. Watchdog Timer Block Diagram External Interface The watchdog timer does not directly interact with any pins of the chip. Internal Interface The watchdog timer is clocked by the system clock .
Page 498: Description Of Operation
Description of Operation When the counter expires, one of three event requests can be generated. Either a reset or an NMI request is issued to the core event controller (CEC) or a general-purpose interrupt request is passed to the system inter- rupt controller (SIC).
Page 499: Register Definitions
Watchdog Timer latch bit in the register is set and can be interrogated by WDRO WDOG_CTL software in case event generation is not enabled. When the watchdog is programmed to generate a reset, it resets the pro- cessor core and peripherals. If the bit in the register was set NOBOOT...
Page 500: Watchdog Status (Wdog_Stat) Register
Register Definitions A valid write to the register also preloads the watchdog counter. WDOG_CNT For added safety, the register can be updated only when the WDOG_CNT watchdog timer is disabled. A write to the register while the WDOG_CNT timer is enabled does not modify the contents of this register. Watchdog Count Register (WDOG_CNT) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16...
Page 501: Watchdog Control (Wdog_Ctl) Register
Watchdog Timer register is a 32-bit unsigned system MMR that must be WDOG_STAT accessed with 32-bit reads and writes. Watchdog Status Register (WDOG_STAT) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset = 0x0000 0000 Watchdog Status[31:16] 15 14 13 12 11 10 Watchdog Status[15:0]...
Page 502: Programming Examples
Programming Examples set whenever the watchdog timer count reaches 0. It can be cleared only by writing a “1” to the bit when the watchdog has been disabled first. Watchdog Control Register (WDOG_CTL) 15 14 13 12 11 10 Reset = 0x0AD0 WDRO - W1C WDEV[1:0] 0 - Watchdog timer has not expired...
Page 503 Watchdog Timer p0.h=hi(SWRST); p0.l=lo(SWRST); r6 = w[p0] (z); CC = bittst(r6, bitpos(RESET_WDOG)); if !CC jump _reset.no_watchdog_reset; /* optionally, warn at system level or host device here */ _reset.no_watchdog_reset: /* optionally, set NOBOOT bit to avoid reboot in case */ p0.h=hi(SYSCR); p0.l=lo(SYSCR);...
Page 504 Programming Examples Listing 12-2. Service Watchdog service_watchdog: [--sp] = p5; p5.h = hi(WDOG_STAT); p5.l = lo(WDOG_STAT); [p5] = r0; p5 = [sp++]; rts; service_watchdog.end: Listing 12-3 is an interrupt service routine that restarts the watchdog. Note that the watchdog must be disabled first. Listing 12-3.
Page 505: Unique Information For The Adsp-Bf50X Processor
Watchdog Timer Unique Information for the ADSP-BF50x Processor None. ADSP-BF50x Blackfin Processor Hardware Reference 12-11...
Page 506 Unique Information for the ADSP-BF50x Processor 12-12 ADSP-BF50x Blackfin Processor Hardware Reference...
Page 507: General-Purpose Counter
Specific Information for the ADSP-BF50x For details regarding the number of GP counters for the ADSP-BF50x product, refer to ADSP-BF504, ADSP-BF504F, ADSP-BF506F Embedded Processor Data Sheet. For GP counter interrupt vector assignments, refer to Table 4-3 on page 4-19 Chapter 4, “System...
Page 508: Overview
Overview GP counter behavior for the ADSP-BF50x that differs from the general information in this chapter can be found at the end of this chapter in the section “Unique Information for the ADSP-BF50x Processor” on page 13-37. Overview The purpose of this interface is to convert pulses from incremental posi- tion encoders into data that is representative of the actual position.
Page 509: Interface Overview
General-Purpose Counter • Zero marker/push button support • Capture event timing in association with general purpose timer • Boundary comparison and boundary setting features • Input pin noise filtering (debouncing) • Flexible error detection/signaling Interface Overview A block diagram of the GP counter is shown in Figure 13-1.
Page 510: Description Of Operation
Description of Operation Description of Operation The GP counter has five modes of operation that are described in this section. With the exception of the timed direction mode, the GP counter can operate with the GP timer block to capture additional timing information (time-stamps) associated with events detected by this block.
Page 511: Binary Encoder Mode
General-Purpose Counter Table 13-1. Quadrature Events and Counting Mechanism –4 –3 –2 –1 CNT_COUNTER Register Value CDG:CUD Inputs It is possible to reverse the count direction of the Gray coded signal. This can be achieved by enabling the polarity inverter of either the pin or pin.
Page 512: Up/Down Counter Mode
Description of Operation Reversing the pin polarity has a different effect for the binary encoder mode than for the quadrature encoder mode. Inverting the polar- ity of the pin only, or inverting both the pins, will result in reversing the count direction. Up/Down Counter Mode In this mode, the counter is incremented or decremented at every active edge of the input pins.
Page 513: Timed Direction Mode
General-Purpose Counter bit in the register. If this bit is cleared, a rising edge CDGINV CNT_CONFIG will decrement the counter. If this bit is set, a falling edge will decrement the counter. Timed Direction Mode In this mode, the counter is incremented or decremented at each SCLK cycle.
Page 514 Functional Description filter NOISY EDGES CUD FILTERED Figure 13-2. Programmable Noise Filtering The filtering mechanism is implemented using counters for each pin. The counter for each pin is initialized from the field of the DPRESCALE register. When a transition is detected on a pin, the corre- CNT_DEBOUNCE sponding counter starts counting up to the programmed number of SCLK...
Page 515: Zero Marker (Push Button) Operation
General-Purpose Counter = 0b10001 DPRESCALE 128  131072  *7.5ns 125829s (approx.) 126ms filter Zero Marker (Push Button) Operation input pin can be used to sense the zero marker output of a rotary device or to detect the pressing of a push button. There are four program- ming schemes which are functional in all counter modes: •...
Page 516: Boundary Comparison Modes
Functional Description interrupt controller, this will generate an interrupt request. The active edge is selected by the bit in the register: CZMINV CNT_CONFIG (rising edge if cleared, falling edge if set to one). • Zero-once mode–This mode is used to perform an initial reset of the counter value when an active zero marker is detected.
Page 517: Control And Signaling Events
General-Purpose Counter • Boundary-zero mode–This mode is similar to the boundary-com- pare mode. In addition to setting the status bits and requesting interrupts, the counter value in the register is also set CNT_COUNTER to zero. • Boundary auto-extend mode–In this mode, the boundary registers are modified by hardware whenever the counter value reaches either of them.
Page 518: Illegal Gray/Binary Code Events
Functional Description acknowledged, the application software is responsible for correct interpre- tation of the events. It is recommended to logically the content of the registers to identify pending interrupts. Inter- CNT_IMASK CNT_STATUS rupt requests are cleared by write-one-to-clear (W1C) operations to the register.
Page 519: Zero-Count Events
General-Purpose Counter Zero-Count Events status bit indicates that the has reached a value CZEROII CNT_COUNTER equal to 0x0000 0000 after an increment or decrement. This bit is not set when the counter value is set to zero by a write to or by set- CNT_COUNTER ting the...
Page 520: Zero Marker Events
Functional Description Zero Marker Events There are three status bits associated with zero CZMII CZMEII CZMZII marker events, as described in “Zero Marker (Push Button) Operation” on page 13-9. Each of these events can optionally generate an interrupt request, if enabled by the corresponding bits in CZMIE CZMEIE...
Page 521: Capturing Counter Interval And Cnt_Counter Read Timing
General-Purpose Counter Typically, this information is sufficient if the speed of GP counter events is known not to reach very low values. Figure 13-3 shows the operation of the GP counter and the GP timer in this mode. TO generates a pulse every time a count event occurs.
Page 522 Functional Description SCLK TIMER_PERIOD CNT_COUNTER TIMER_COUNTER TIMER_PERIOD BUFFER TIMER_WIDTH BUFFER TIMER_PERIOD TIMER_WIDTH Measurement reports available Figure 13-3. Operation With GP Timer Module TO is low, again because = 0). Both registers are updated at PULSE_HI every rising edge of the TO signal (because = 0).
Page 523 General-Purpose Counter  Restrictions apply to the use of the TO signal in terms of speed. Therefore, the user must take care to not operate at very high count events. For instance, if is incremented/decremented CNT_COUNTER every cycle (timed direction mode), the TO signal is SCLK incorrect.
Page 524: Programming Model
Programming Model Programming Model In a typical application, the user will initialize the GP counter for the desired mode, without enabling it. Normally the events of interest will be processed using interrupts rather than polling the status bit. In that case, clear all status bits and activate the generation of interrupt requests with register.
Page 525: Counter Configuration Register (Cnt_Config)
General-Purpose Counter Table 13-3. Counter Module Register Overview (Cont’d) Register Name Width PAB Operation Reset Value CNT_MAX 32 bits R/W (16/32 bits) 0x0000 0000 CNT_MIN 32 bits R/W (16/32 bits) 0x0000 0000 Counter Configuration Register (CNT_CONFIG) This register (Figure 13-5) is used to configure counter modes and input pins, as well as to enable the peripheral.
Page 526: Counter Interrupt Mask Register (Cnt_Imask)
Registers Counter Interrupt Mask Register (CNT_IMASK) This register (Figure 13-6) is used to enable interrupt request generation from each of the eleven events. It can be accessed at any time with 16-bit read and write operations. For explanations of the register bits, refer to “Control and Signaling Events”...
Page 527: Counter Command Register (Cnt_Command)
General-Purpose Counter Counter Status (CNT_STATUS) Register 14 13 12 11 10 Reset = 0x0000 CZMZIE ICII (Counter zeroed by zero marker) (W1C) (Illegal Gray/binary code interrupt) (W1C) CZMEII UCII (Zero marker error interrupt) (W1C) (Upcount interrupt) CZMII DCII (CZM pin interrupt/ Push-button interrupt) (W1C) (Downcount interrupt) (W1C) MINCII CZEROII...
Page 528 Registers registers to create new boundary limits. This is per- CNT_MAX CNT_MIN formed by setting the bits. Alternatively, the W1LMAX_CNT W1LMIN_CNT counter can be loaded from via the CNT_MAX CNT_MIN W1LCNT_MAX bits. It is also possible to transfer the current value W1LCNT_MIN CNT_MAX...
Page 529: Counter Debounce Register (Cnt_Debounce)
General-Purpose Counter Counter Command (CNT_COMMAND) Register 14 13 12 11 10 Reset = 0x0000 W1ZMONCE (Write one to enable single Zero marker W1LCNT_ZERO clear CNT_COUNT action) (W1A/R) (Write one to zero CNT_COUNTER) (W1A) W1LMAX_MIN W1LCNT_MIN (Write one to copy former CNT_MIN to new (Write 1 to load CNT_COUNTER CNT_MAX) (W1A) from CNT_MIN) (W1A)
Page 530: Counter Count Value Register (Cnt_Counter)
Registers Counter Debounce (CNT_DEBOUNCE) Register 14 13 12 11 10 Reset = 0x0000 DPRESCALE (DEBOUNCE DELAY) 00000: 1 x 128 SCLK cycles 00001: 2 x 128 SCLK cycles 00010: 4 x 128 SCLK cycles 00011: 8 x 128 SCLK cycles 00100: 16 x 128 SCLK cycles 00101: 32 x 128 SCLK cycles 00110: 64 x 128 SCLK cycles...
Page 531: Counter Boundary Registers (Cnt_Min And Cnt_Max)
General-Purpose Counter Counter Count Value (CNT_COUNTER) Register 31 30 29 28 27 26 Reset = 0x0000 0000 Count Value 14 13 12 11 10 Count Value Figure 13-10. Counter Count Value Register Counter Boundary Registers (CNT_MIN and CNT_MAX) These registers (Figure 13-11 Figure 13-12) hold the 32-bit,...
Page 532 Registers Counter Maximal Count (CNT_MAX) Register 31 30 29 28 27 26 Reset = 0x0000 0000 CNT_MAX (Counter Max) 14 13 12 11 10 CNT_MAX (Counter Max) Figure 13-11. Counter Maximal Count Register Counter Minimal Count (CNT_MIN) Register 31 30 29 28 27 26 Reset = 0x0000 0000 CNT_MIN[31:16] (Counter Min)
Page 533: Programming Examples
General-Purpose Counter Programming Examples Listing 13-1 illustrates how to initialize the GP counter for various modes. The required interrupts are first unmasked. The GP counter is then con- figured for the required mode of operation. Note that at this point we do not yet enable the counter.
Page 534 Programming Examples | nCUDINV /* Polarity of CUD pin */ | nCDGINV /* Polarity of CDG Pin */ | nDEBE /* Disable the debounce */ | nCNTE (z); /* Disable the counter */ w[P5] = R5; /* Zero the CNT_COUNT, CNT_MIN and CNT_MAX registers This is optional as after reset they are default to zero */ P5.H = hi(CNT_COMMAND);...
Page 535 General-Purpose Counter GP counter is enabled. This example can be easily tailored to processors with different SIC register mappings. Listing 13-2. Setting Up the Interrupts for the GP Counter /* Assign the CNT interrupt to IVG11 */ P5.H = hi(SIC_IAR3); P5.L = lo(SIC_IAR3);...
Page 536 Programming Examples R5 = [P5]; bitset(R5, bitpos(IRQ_CNT)); [P5] = R5; /* Enable the counter */ P5.H = hi(CNT_CONFIG); P5.L = lo(CNT_CONFIG); R5 = w[P5](z); bitset(R5, bitpos(CNTE)); w[P5] = R5.L; Using the same assumptions from the previous example, Listing 13-3 illustrates a sample interrupt handler that is responsible for servicing the GP counter interrupts.
Page 537 General-Purpose Counter SSYNC; /* Restore from stack */ (R7:0, P5:0) = [SP++]; ASTAT = [SP++]; RETS = [SP++]; RTI; /* Exit the interrupt service routine */ _IVG11_handler.end: _IVG11_handler.counter: /* Stack management */ [--SP] = RETS; [--SP] = (R7:0, P5:0); /* Determine what counter interrupts we wish to service */ R5 = w[P5](z);...
Page 538 Programming Examples /* insert illegal code handler here */ _IVG11_handler.counter.illegal_code.end: _IVG11_handler.counter.up_count: CC = bittst(R5, bitpos(UCII)); IF !CC JUMP _IVG11_handler.counter.down_count; /* Clear the serviced request */ R6 = UCII (z); w[P5] = R6; /* insert up count handler here */ _IVG11_handler.counter.up_count.end: _IVG11_handler.counter.down_count: CC = bittst(R5, bitpos(DCII));...
Page 539 General-Purpose Counter R6 = MINCII (z); w[P5] = R6; /* insert min count handler here */ _IVG11_handler.counter.min_count.end: _IVG11_handler.counter.max_count: CC = bittst(R5, bitpos(MAXCII)); IF !CC JUMP _IVG11_handler.counter.b31_overflow; /* Clear the serviced request */ R6 = MAXCII (z); w[P5] = R6; /* insert max count handler here */ _IVG11_handler.counter.max_count.end: _IVG11_handler.counter.b31_overflow: CC = bittst(R5, bitpos(COV31II));...
Page 540 Programming Examples IF !CC JUMP _IVG11_handler.counter.count_to_zero; /* Clear the serviced request */ R6 = COV15II (z); w[P5] = R6; /* insert bit 15 overflow handler here */ _IVG11_handler.counter.b15_overflow.end: _IVG11_handler.counter.count_to_zero: CC = bittst(R5, bitpos(CZEROII)); IF !CC JUMP _IVG11_handler.counter.czm; /* Clear the serviced request */ R6 = CZEROII (z);...
Page 541 General-Purpose Counter _IVG11_handler.counter.czm_error: CC = bittst(R5, bitpos(CZMEII)); IF !CC JUMP _IVG11_handler.counter.czm_zeroes_counter; /* Clear the serviced request */ R6 = CZMEII (z); w[P5] = R6; /* insert czm error handler here */ _IVG11_handler.counter.czm_error.end: _IVG11_handler.counter.czm_zeroes_counter: CC = bittst(R5, bitpos(CZMZII)); IF !CC JUMP _IVG11_handler.counter.all_serviced; /* Clear the serviced request */ R6 = CZMZII (z);...
Page 542 Programming Examples “General-Purpose Ports” for information regarding which GP timer(s) are associated with which GP counter module(s) for your device. The timer is configured for mode, and the period between the last two suc- WDTH_CAP cessive counter events is read from within the up count interrupt handler that was provided in Listing 13-3 on page 13-30.
Page 543: Unique Information For The Adsp-Bf50X Processor
General-Purpose Counter P5.L = lo(TIMER7_PERIOD); R5 = [P5]; P5.H = hi(_event_period); P5.L = lo(_event_period); [P5] = R5; _IVG11_handler.counter.up_count.end: Unique Information for the ADSP-BF50x Processor None. ADSP-BF50x Blackfin Processor Hardware Reference 13-37...
Page 544 Unique Information for the ADSP-BF50x Processor 13-38 ADSP-BF50x Blackfin Processor Hardware Reference...
Page 545: 14 Pwm Controller
Specific Information for the ADSP-BF50x For details regarding the number of PWMs for the ADSP-BF50x product, refer to ADSP-BF504, ADSP-BF504F, ADSP-BF506F Embedded Processor Data Sheet. For PWM Controller interrupt vector assignments, refer to Table 4-3 on page 4-19 Chapter 4, “System...
Page 546 Overview induction motor (ACIM) or permanent magnet synchronous motor (PMSM) control. In addition, the PWM block contains functions that considerably simplify the generation of the required PWM switching patterns for control of electronically commutated motors (ECMs) or brushless dc motors (BDCMs).
Page 547 PWM Controller PWM_STAT2 PWM DUTY CONFIGURATION CYCLE REGISTERS REGISTERS PWM_CHA PWM_TM PWM_DT PAB BUS PWM_SEG[5:0] PWM_GATE PWM_CHB PWM_SEG[8:6] PWM_CTRL PWM_CHC PWM_AH PWM_AL DEAD THREE-PHASE OUTPUT GATE PWM_BH TIME PWM TIMING CONTROL DRIVE CONTROL PWM_BL UNIT UNIT UNIT UNIT PWM_CH PWM_CL SYNC SR POL SYNC SR...
Page 548 Overview The PWM Controller is driven by a clock, whose period is t . The SCLK PWM generator produces three pairs ( PWM_AH PWM_AL PWM_BH PWM_BL , and ) of PWM signals on the six PWM output pins. There PWM_CH PWM_CL are three high-side drive signals ( , and...
Page 549 PWM Controller -PWMTM/2 +PWMTM/2 +PWMTM/2 COUNT PWMCHA=PWMCHB PWMCHA=PWMCHB PWM_AH PWM_AL 2*PWMDT PWM_BH PWM_BL PWM_CH PWM_CL Figure 14-2. Active Low PWM Signals for ECM Control high-frequency chopping signal, which provides an simple interface to pulse transformers. The features of gate-drive-chopping mode are con- trolled by the register.
Page 550 Overview The PWM generator is capable of operating in two distinct modes: • Single-Update Mode. In single-update mode, duty cycle values are programmable only once per PWM period; resultant PWM pat- terns are symmetrical about the mid-point of the PWM period. •...
Page 551 PWM_TRIP pin in these cases. For these and other questions about pin multi- plexing, see ADSP-BF504, ADSP-BF504F, ADSP-BF506F Embedded Processor Data Sheet. The PWM unit is capable of generating two different interrupt types. One...
Page 552: General Operation
General Operation shut-down action. Both interrupts are generated only when the corre- sponding enable bits ( ) are set in the PWMSYNCINT_EN PWMTRIPINT_EN register. PWM_CTRL register provides status information about the PWM sys- PWM_STAT tem. In particular, the state of the pin ( bit), PWM_TRIP...
Page 553: Functional Description
PWM Controller read to determine polarity, and whether switched reluctance (SR) mode bit) is enabled, and whether an external trip situation is prevent- PWM_SR ing the correct start-up of the PWM Controller. An active external trip event must be resolved prior to PWM startup. The register is PWM_CTRL then written to define the major operating mode and to enable the PWM...
Page 554: Three-Phase Pwm Timing Unit And Dead Time Control Unit
Functional Description • “PWM Duty Cycle (PWM_CHA, PWM_CHB, and PWM_CHC) Registers” on page 14-14 • “Special Consideration for PWM Operation in Over-Modulation” on page 14-20 • “Three-Phase PWM Timing Unit Operation” on page 14-22 • “Effective PWM Accuracy” on page 14-24 •...
Page 555 PWM Controller Controller is t . Therefore, for a 100 MHz system clock ( ), f SCLK SCLK SCLK the fundamental time increment (t ) is 10 ns. The value written to the SCLK register is effectively the number of t clock increments in half PWM_TM SCLK...
Page 556: Pwm Switching Dead Time (Pwm_Dt) Register
Functional Description PWM Switching Dead Time (PWM_DT) Register The second important parameter that must be set up in the initial config- uration of the PWM Controller is the switching dead time. This is a short delay introduced between turning off one PWM signal (for example, and turning on the complementary signal (for example, ).
Page 557: Pwm Operating Mode (Pwm_Ctrl And Pwm_Stat)
PWM Controller PWM Operating Mode (PWM_CTRL and PWM_STAT) Registers The PWM Controller can operate in two distinct modes: single-update mode and double-update mode. The mode is determined by the state of bit of the register. When this bit is cleared, the PWM PWM_DBL PWM_CTRL Controller operates in single-update mode.
Page 558: Pwm Duty Cycle Pwm_Cha, Pwm_Chb, And Pwm_Chc) Registers
Functional Description information is provided by the bit of the register, PWM_PHASE PWM_STAT which is cleared during operation in the first half of each PWM period (between the rising edge of the original pulse and the rising edge PWM_SYNC of the second pulse introduced in double-update mode).
Page 559 PWM Controller Each duty cycle register range is from (–PWMTM/2 – PWMDT) to (+PWMTM/2 + PWMDT), which, by definition, is scaled such that a value of 0 represents a 50% PWM duty cycle. The switching signals produced by the Three-Phase PWM Timing Unit are also adjusted to incorporate the programmed dead time value in the register by programming active low polarity in .
Page 560 Functional Description -PWMTM/2 +PWMTM/2 +PWMTM/2 COUNT PWMCHA PWMCHA PWM_AH PWM_AL 2*PWMDT 2*PWMDT PWMSYNC_OUT PWMTM PWMTM PWM_PHASE Figure 14-3. Typical PWM Outputs of Three-Phase Timing Unit in Single-Update Mode (Active-Low Waveforms) The resultant on-times (active low) of the PWM signals over the full PWM period (two half periods) produced by the Three-Phase PWM Tim- ing Unit and illustrated in Figure...
Page 561 PWM Controller      t  – PWMTM PWMCHA PWMDT SCLK   Range of T 0 2 PWMTM SCLK and the corresponding duty cycles are: – PWMCHA PWMDT ----------- - -- - --------------------------------------------------------- - PWMTM PWMCHA PWMDT --------- - -- -...
Page 562 Functional Description -PWMTM -PWMTM +PWMTM +PWMTM COUNT PWMCHA PWMCHA PWM_AH PWM_AL 2*PWMDT 2*PWMDT PWMSYNC_OUT PWMTM PWMTM PWM_PHASE Figure 14-4. Typical PWM Outputs of Three-Phase Timing Unit in Double-Update Mode (Active Low Waveforms) In general, the on-times (active low) of the PWM signals over the full PWM period in double-update mode can be defined as: PWMTM PWMTM...
Page 563 PWM Controller   t  PWMTM PWMTM SCLK where subscript 1 refers to the value of that register during the first half cycle and subscript 2 refers to the value during the second half cycle. The corresponding duty cycles are: ...
Page 564: Special Consideration For Pwm Operation In Over-Modulation
Functional Description Special Consideration for PWM Operation in Over-Modulation The Three-Phase PWM Timing Unit can produce PWM signals with variable duty-cycle values at the PWM output pins. At the extremities of the modulation process, both 0% and 100% modulation (termed full off mode and full on mode, respectively) are possible.
Page 565 PWM Controller appropriate for safety, emergency dead-time is inserted to prevent shoot-through conditions. The insertion of additional emergency dead time into one of the PWM signals of a given pair during these transitions is necessary only when both PWM signals are required to toggle within a dead time of each other. The additional emergency dead time delay is inserted into the PWM sig- nal that is toggling into the “on”...
Page 566: Three-Phase Pwm Timing Unit Operation
Functional Description -PWMTM/2 +PWMTM/2 +PWMTM/2 COUNT PWMCHA PWM_AH PWM_AL 2*PWMDT PWM_AH 2*PWMDT PWM_AL DEADTIME INSERTED HERE Figure 14-5. Examples of Transitioning from Normal Modulation to Full On Mode (A) or Full Off Mode (B) Three-Phase PWM Timing Unit Operation The internal operation of the PWM Controller is controlled by the Three-Phase PWM Timing Unit, which is clocked at the system clock rate with period t .
Page 567 PWM Controller count direction changes, and the unit increments from -PWMTM/2 to the +PWMTM/2 value. PWM TIMER DECREMENTS FROM PWM TIMER INCREMENTS FROM PWMTM÷2 TO –PWMTM÷2 –PWMTM÷2 TO PWMTM÷2 PWMTM÷2 –PWMTM÷2 PWM_SYNC_OUT SINGLE-UPDATE MODE PWM_SYNC_OUT DOUBLE_UPDATE MODE PWM_PHASE Figure 14-6. Operation of Internal PWM Timer Figure 14-6 also shows the PWM SYNC pulses during single-update mode and double-update mode.
Page 568: Effective Pwm Accuracy
Functional Description Effective PWM Accuracy The PWM Controller has 16-bit resolution, but accuracy depends on the PWM period. In single-update mode, the same values of PWM_CHA , and define the on-times in both half cycles of the PWM PWM_CHB PWM_CHC period.
Page 569: Switched Reluctance Mode
PWM Controller Switched Reluctance Mode A general-purpose mode utilizing independent edge placement of upper and lower signals of each of the three PWM channels is incorporated into the Three-Phase PWM Timing Unit. This mode is provided for SR motor operation and is described in detail in “Switched Reluctance (SR) Mode”...
Page 570: Mode Bits (Polarity And Srmode)
Functional Description Mode Bits (POLARITY and SRMODE) are programmable bits of the PWM_POLARITY PWM_SRMODE PWM_CTRL register.  The incorrect programming of these two mode-select signals can have destructive consequences on the external power inverter con- nected to the PWM unit. Since PWM_POLARITY PWM_SRMODE software programmable bits, accidental power inverter...
Page 571: Brushless Dc Motor (Electronically Commutated Motor) Control
PWM Controller Brushless DC Motor (Electronically Commutated Motor) Control In the control of an electronically commutated motor (ECM), only two inverter legs are switched at any time. Often, the high-side device in one leg must be switched on at the same time as the low-side driver in a second leg.
Page 572 Functional Description -PWMTM/2 +PWMTM/2 +PWMTM/2 COUNT PWMCHA=PWMCHB PWMCHA=PWMCHB PWM_AH PWM_AL 2*PWMDT PWM_BH PWM_BL PWM_CH PWM_CL Figure 14-7. Example of Active Low Signals for ECM Control For the situation illustrated in Figure 14-7, an appropriate value for the register is 0x00A7. In normal ECM operation, each inverter leg is PWM_SEG disabled for certain lengths of time, such that the register is...
Page 573: Gate Drive Unit
PWM Controller Gate Drive Unit The Gate Drive Unit is described in the following sections: • “High-Frequency Chopping” • “PWM Polarity Control” on page 14-30 High-Frequency Chopping The Gate Drive Unit of the PWM Controller simplifies the design of isolated gate drive circuits for PWM inverters. If a transformer-coupled power device gate drive amplifier is used, the active PWM signal must be chopped at a high frequency.
Page 574: Pwm Polarity Control
Functional Description and the chopping frequency is therefore an integral subdivision of the system clock frequency: SCLK ------------------------------------------------- -      chop GDCLK value may range from 0 to 255, which corresponds to a pro- GDCLK grammable chopping frequency rate from 97.7 kHz to 25 MHz for a 100 MHz f rate.
Page 575: Output Control Feature Precedence
PWM Controller this bit to 0 selects active low PWM outputs, such that a low level is inter- preted as a command to turn on the associated power device. Conversely, setting the bit to 1 selects active high PWM outputs, such PWM_POLARITY that a high level at the PWM outputs turns on the associated power devices.
Page 576 Functional Description Conversely, if the bit is low and SR mode is enabled, the PWM_SRMODE bit of register is cleared. PWM_SR PWM_STAT  Since this is a software programmable bit, be careful not to write it to an active state in a non-SR mode system and cause shoot-through at the power inverters, possibly leading to an unsafe situation.
Page 577 PWM Controller Figure 14-9 shows the four SR mode types as active-high PWM output signals, and Table 14-2 describes the four mode types. -PWMTM/2 +PWMTM/2 +PWMTM/2 PWMCHA COUNT PWMCHA PWM_AH HARD CHOP PWMCHAL PWMCHAL PWM_AL PWMCHA PWMCHA PWM_AH ALTER- NATE PWMCHAL PWMCHAL CHOP...
Page 578: Pwm Sync Operation
Functional Description Table 14-2. Switched Reduction Mode (SR Mode) Types Mode Description Hard Contains independently programmed rising edges of channels’ high and low signals chop in the same PWM half cycle, and both contain independently programmed falling edges in the next PWM half cycle. The duty register is used for the high PWM_CHA channel, and the...
Page 579: Internal Pwm Sync Generation
PWM Controller Internal PWM SYNC Generation The PWM Controller produces an output PWM synchronization pulse at a rate equal to the PWM switching frequency in single-update mode and at twice the PWM frequency in double-update mode. This pulse is avail- able for external use at the pin.
Page 580: Pwm Shutdown And Interrupt Control Unit
Functional Description The latency from to the effect in PWM outputs is 3 cycles PWM_SYNC SCLK in synchronous mode and 5 cycles in asynchronous mode. SCLK  In external sync pulse mode, do not allow changes in PWM_SYNCSEL (which selects between asynchronous/synchronous external sync pulse) ±...
Page 581: Pwm Registers
PWM Controller  The dead time counters will be reset when a trip occurs, and the user is expected to restart the PWM only after waiting the required dead time. If restarting a PWM immediately after trip, for high dead time period cases, the dead time will not be met. ...
Page 582: Pwm Control (Pwm_Ctrl) Register
PWM Registers Table 14-3. PWM Registers (Cont’d) Name Description PWM_SYNCWT PWM sync pulse width control on page 14-47 PWM_CHAL PWM channel AL duty control (SR mode only) on page 14-47 PWM_CHBL PWM channel BL duty control (SR mode only) on page 14-47 PWM_CHCL PWM channel CL duty control (SR mode only) on page 14-47...
Page 583 PWM Controller Table 14-4. PWM_CTRL Register Name Function Type Default PWM_EN PWM enable Hardware modifiable bit. 0 = disabled 1 = enabled reset by PWM_TRIP PWM_SYNC_EN PWM sync enable 0 = disabled 1 = enabled PWM_DBL Double-update mode 0 = single-update mode 1 = double-update mode PWM_EXTSYNC External sync...
Page 584: Pwm Status (Pwm_Stat) Register
PWM Registers PWM Status (PWM_STAT) Register register provides status information regarding PWM opera- PWM_STAT tion. Bit diagrams and descriptions are provided in Figure 14-11 Table 14-5. PWM Status Register (PWM_STAT) 15 14 13 12 11 10 Reset = 0x0006 Reserved PWM_PHASE PWM_SYNCINT PWM_POL...
Page 585: Pwm Period (Pwm_Tm) Register
PWM Controller Table 14-5. PWM_STAT Register (Cont’d) Name Function Type Default PWM_SYNCINT PWM sync interrupt R/W1C 0 15:10 Reserved PWM Period (PWM_TM) Register register controls the switching frequency of the generated PWM_TM PWM patterns. Bit diagrams and descriptions are provided in Figure 14-12 Table 14-6.
Page 586: Pwm Dead Time (Pwm_Dt) Register
PWM Registers PWM Dead Time (PWM_DT) Register register controls the dead time interval of the generated PWM PWM_DT patterns. Bit diagrams and descriptions are provided in Figure 14-13 Table 14-7. PWM Dead Time Register (PWM_DT) 15 14 13 12 11 10 Reset = 0x0000 Reserved PWM_DT...
Page 587: Pwm Channel A, B, C Duty Control (Pwm_Cha, Pwm_Chb, Pwm_Chc) Registers
PWM Controller PWM Chopping Control Register (PWM_GATE) 15 14 13 12 11 10 Reset = 0x0000 GDCLK Reserved CHOPLO CHOPHI Figure 14-14. PWM Chopping Control Register Table 14-8. PWM_GATE Register Name Function Type Default GDCLK PWM gate chopping period (unsigned) CHOPHI Gate chopping enable high side CHOPLO...
Page 588 PWM Registers PWM Channel A Duty Control Register (PWM_CHA) 15 14 13 12 11 10 Reset = 0x0000 PWMCHA Figure 14-15. PWM Channel A Duty Control Register Table 14-9. PWM_CHA Register Name Function Type Default 15:0 PWMCHA Channel A duty (two’s complement) RW PWM Channel B Duty Control Register (PWM_CHB) 15 14 13 12 11 10 Reset = 0x0000...
Page 589: Pwm Crossover And Output Enable (Pwm_Seg) Register
PWM Controller Table 14-11. PWM_CHC Register Name Function Type Default 15:0 PWMCHC Channel C duty (two’s complement) RW PWM Crossover and Output Enable (PWM_SEG) Register register controls output enabling of the high-side and PWM_SEG low-side PWM outputs, and it also permits configuration of crossover mode for each output pair.
Page 590 PWM Registers Table 14-12. PWM_SEG Register Name Function Type Default CH_EN CH output enable 1 = disabled 0 = enabled CL_EN CL output enable 1 = disabled 0 = enabled BH_EN BH output enable 1 = disabled 0 = enabled BL_EN BL output enable 1 = disabled...
Page 591: Pwm Sync Pulse Width Control (Pwm_Syncwt)
PWM Controller PWM Sync Pulse Width Control (PWM_SYNCWT) Register register allows programming of the PWM_SYNC pulse PWM_SYNCWT width. Bit diagrams and descriptions are provided in Figure 14-19 Table 14-13. PWM Sync Pulse Width Control Register (PWM_SYNCWT) 15 14 13 12 11 10 Reset = 0x03FF Reserved PWMSYNCWT...
Page 592 PWM Registers PWM Channel AL Duty Control Register (PWM_CHAL) 15 14 13 12 11 10 Reset = 0x0000 PWM_CHAL Figure 14-20. PWM Channel AL Duty Control Register Table 14-14. PWM_CHAL Register Name Function Type Default 15:0 PWMCHAL Channel A duty (two’s complement) PWM Channel BL Duty Control Register (PWM_CHBL) 15 14 13 12 11 10 Reset = 0x0000...
Page 593: Pwm Low Side Invert (Pwm_Lsi) Register
PWM Controller Table 14-16. PWM_CHCL Register Name Function Type Default 15:0 PWM_CHCL Channel C duty (two’s complement) RW PWM Low Side Invert (PWM_LSI) Register register is used for specifying switched reluctance (SR) chop PWM_LSI modes. Bit diagrams and descriptions are provided in Figure 14-23 Table 14-17.
Page 594: Unique Information For The Adsp-Bf50X Processor
Unique Information for the ADSP-BF50x Processor debug operation. Bit diagrams and descriptions are provided in Figure 14-24 Table 14-18. PWM Simulation Status Register (PWM_STAT2) 15 14 13 12 11 10 Reset = 0x0000 Reserved PWM_AL PWM_AH PWM_BL PWM_BH PWM_CL PWM_CH Figure 14-24.
Page 595: 15 Uart Port Controllers
15 UART PORT CONTROLLERS This chapter describes the universal asynchronous receiver/transmitter (UART) modules and includes the following sections: • “Overview” • “Interface Overview” on page 15-3 • “Description of Operation” on page 15-5 • “Programming Model” on page 15-22 • “UART Registers”...
Page 596: Features
Overview Features Each UART includes these features: • 5 – 8 data bits • 1 or 2 stop bits (1 1/2 in 5-bit mode) • Even, odd, and sticky parity bit options • Additional 4-stage receive FIFO with programmable threshold interrupt •...
Page 597: Interface Overview
UART Port Controllers Interface Overview Figure 15-1 shows a simplified block diagram of one UARTx module and how it interconnects to the Blackfin architecture and to the outside world. BLACKFIN SIC CONTROLLER DMA CONTROLLER 16/32 UARTx UARTx_IER UARTx_GCTL CLEAR UARTxCTS UARTx_LCR UARTx_LSR UARTx_MSR...
Page 598 Interface Overview EIA-232, EIA-422, 4-wire EIA-485) or half duplex (for example, 2-wire EIA-485, LIN) standards. Additionally, each UART features a pair of (clear to send, input) and (request to send, output) sig- UARTxCTS UARTxRTS nals for hardware flow control. All UART signals are multiplexed and compete with other functions at pin level.
Page 599: Internal Interface
UART Port Controllers Internal Interface The UARTs are DMA-capable peripherals with support for separate TX and RX DMA master channels. They can be used in either DMA or pro- grammed non-DMA mode of operation. The non-DMA mode requires software management of the data flow using either interrupts or polling. The DMA method requires minimal software intervention as the DMA engine itself moves the data.
Page 600: Uart Transfer Protocol
Description of Operation UART Transfer Protocol UART communication follows an asynchronous serial protocol, consisting of individual data words. A word has 5 to 8 data bits. All data words require a start bit and at least one stop bit. With the optional parity bit, this creates a 7- to 12-bit range for each word.
Page 601: Uart Transmit Operation
UART Port Controllers IrDA support is enabled by setting the bit in the register. IREN UARTx_GCTL The IrDA application requires external transceivers. UART Transmit Operation Receive and transmit paths operate completely independently except that the bit rate and the frame format are identical for both transfer directions. Transmission is initiated by writes to the UARTx_THR register.
Page 602: Uart Receive Operation
Description of Operation bit goes high again and indicates that all pending transmit operation TEMT has finished. At that time it is safe to disable the bit or to three-state UCEN off-chip line drivers. An interrupt can be generated by that time either through the status interrupt channel when the bit is set.
Page 603 UART Port Controllers If enabled by the bit in the register, the flag requests ERBFI UARTx_IER an interrupt on the dedicated output. This signal is routed through RXREQ the DMA controller. If the associated DMA channel is enabled, the RXREQ signal functions as a DMA request, otherwise the DMA controller simply forwards it to the SIC interrupt controller.
Page 604: Hardware Flow Control
Description of Operation line. Spurious pulses of less than two times the sampling clock period are disregarded. Normally, every incoming bit is sampled at exactly the 7th, 8th and 9th sample clock. If, however, the EDBO bit is set to 1 to achieve better bit rate granularity and accuracy as required at high operation speeds, the bits are one roughly sampled at 7/16th, 8/16th and 9/16th of their period.
Page 605 UART Port Controllers data transfer is bidirectional, the handshake is as shown in Figure 15-3. BLACKFIN OTHER UART UARTx DEVICE UARTxTX UARTxRX UARTxRTS UARTxCTS Figure 15-3. UART Hardware Flow Regardless of whether working in DMA or non-DMA mode, the receiver can deassert the signal to indicate that its receive buffer is getting UARTxRTS...
Page 606 Description of Operation hardware pauses transmission if the bit is zero. If the UARTxCTS UARTxCTS input is deasserted, the transmitter still completes transmission of the data work currently held in the internal register, but does not continue TSRx with the data in .
Page 607: Irda Transmit Operation
UART Port Controllers IrDA Transmit Operation To generate the IrDA pulse transmitted by the UART, the normal NRZ output of the transmitter is first inverted if the bit is cleared, so a 0 TPOLC is transmitted as a high pulse of 16 UART clock periods and a 1 is trans- mitted as a low pulse for 16 UART clock periods.
Page 608: Irda Receive Operation
Description of Operation IrDA Receive Operation The IrDA receiver function is more complex than the transmit function. The receiver must discriminate the IrDA pulse and reject noise. To do this, the receiver looks for the IrDA pulse in a narrow window centered around the middle of the expected pulse.
Page 609 UART Port Controllers The polarity of receive data is selectable, using the bit. Figure 15-5 IRPOL gives examples of each polarity type. • = 0 assumes that the receive data input idles 0 and each IRPOL active 1 transition corresponds to a UART NRZ value of 0. •...
Page 610: Interrupt Processing
Description of Operation Interrupt Processing Each UART module has three interrupt outputs. One is dedicated for transmission, one for reception, and the third is used to report status events. As shown in Figure 15-1 on page 15-3, the transmit and receive requests are routed through the DMA controller.
Page 611 UART Port Controllers DMA request. This way, no special handling of the first character is required when transmission of a string is initiated. Simply set the ETBEI bit and let the interrupt service routine load the first character from mem- ory and write it to the register in the normal manner.
Page 612: Bit Rate Generation
Description of Operation The receive FIFO count interrupt is enabled by the bit in the ERFCI register. If set, a status interrupt is generated when the UARTx_IER_SET is active. The bit indicates a receive buffer threshold level. If the RFCS RFCS bit in the register is cleared, software can safely read two...
Page 613 UART Port Controllers ple clock if the bit in the register is set, so that the EDBO UARTx_GCTL following applies: SCLK ---------------------------------------------------- - BIT RATE   –  1 EDB0 Divisor Divisor = 65,536 when UARTx_DLL UARTx_DLH Table 15-2 provides example divide factors required to support most stan- dard baud rates.
Page 614: Autobaud Detection
Description of Operation however, a disadvantage—the power dissipation is higher. Also the sample points may not be that accurate. It is recommended to use =1 mode only when bit rate accuracy is not acceptable in EDBO =0 mode. EDBO =1 mode is not intended to increase operation speed EDBO beyond the electrical limitations of the asynchronous UART trans- fer protocol.
Page 615 UART Port Controllers operation—all derived from —the pulse widths can be used to calcu- SCLK late the bit rate divider for the UART by using the following formula: · TIMERx _WIDTH ----------------------------------------------------------------------------------------------------------------- DIVISOR   – 1 EDB0  Number of captured UART bits In order to increase the number of timer counts and therefore the resolu- tion of the captured signal, it is recommended not to measure just the pulse width of a single bit, but to enlarge the pulse of interest over more...
Page 616: Programming Model
Programming Model falling edge of the start bit and the falling edge after bit 6. Since this period encloses 8 bits, apply the following: • Divisor = >> 7 if TIMERx_PERIOD EDB0 • Divisor = >> 3 if TIMERx_PERIOD EDB0 STOP PERIOD Figure 15-7.
Page 617 UART Port Controllers when it is not empty overwrites the register with the new value and the previous character is never transmitted. flag signals when new data is available in . This flag is UARTx_RBR cleared automatically when the processor reads from .
Page 618: Dma Mode
Programming Model To reduce interrupt frequency on the receive side in non-DMA mode, the status interrupt may be used as an alternative to the regular ERFCI ERBFI receive interrupt. Hardware ensure that at least two (if =0) or four (if RFIT =1) words are available in the receive buffer by the time the interrupt RFIT...
Page 619: Mixing Modes
UART Port Controllers control bit only when the bit is set, otherwise up to four ETBEI SYNC data bytes might be lost. When the bit is set in the register, an initial transmit ETBEI UARTx_IER_SET DMA request is issued immediately. It is common practice to clear the bit by the DMA’s service routine.
Page 620: Uart Registers
UART Registers the interrupt occurs, software can write new data into the regis- UARTx_THR ter as soon as the bit permits. If the bit cannot be set, software THRE SYNC can poll the bit instead. DMA_RUN When switching from non-DMA to DMA operation, take care that the very first DMA request is issued properly.
Page 621 UART Port Controllers additional 4-stage receive FIFO buffer the receive shift register ( ). The shift registers are not directly accessible by software. Table 15-3. ADSP-BF50x versus ADSP-BF52x UART Register ADSP-BF50x ADSP-BF52x Register Name Name Address Offset Address Offset UARTx_DLL 0x00 0x00, DLAB=1 UART divisor latch low byte registers on page 15-43...
Page 622: Uartx_Lcr Registers
UART Registers UARTx_LCR Registers The line control ( ) registers, shown in Figure 15-8, control the UARTx_LCR format of received and transmitted character frames. UART Line Control Registers (UARTx_LCR) 15 14 13 12 11 10 For memory- Reset = 0x0000 mapped addresses, SB (Set Break)
Page 623 UART Port Controllers bit controls how many stop bits are appended to transmitted data. When , one stop bit is transmitted. If is non zero, STB=0 STB=1 instructs the transmitter to add one additional stop bit, two stop bits in total.
Page 624 UART Registers Table 15-5. UART Parity (Cont’d) Data (hex) Data (binary, LSB Parity first) 0x57 1110 1010 If set, the bit forces the pin to low asynchronously, regardless UARTxTX of whether or not data is currently transmitted. It functions even when the UART clock is disabled.
Page 625: Uartx_Mcr Registers
UART Port Controllers UARTx_MCR Registers The modem control ( ) registers control the UART port, as UARTx_MCR shown in Figure 15-9. Partial modem functionality is supported to allow for hardware flow control and loopback mode. UART Modem Control Registers (UARTx_MCR) 15 14 13 12 11 10 Reset = 0x0000 For memory-...
Page 626 UART Registers Table 15-6. UART Modem Control Register Memory-Mapped Addresses Register Name Memory-Mapped Address UART0_MCR 0xFFC0 0410 UART1_MCR 0xFFC0 2010 The receive FIFO interrupt threshold ( ) bit controls the timing of the RFIT status bit. If =0, the receive threshold is two. If =1, the RFCS RFIT...
Page 627: Uartx_Lsr Registers
UART Port Controllers from being continued to the TSR shift register. When =1, the ACTS XOFF bit is ignored. When =0, the state of the input signal is ignored. ACTS The polarities of the pins can be programmed UARTxCTS UARTxRTS using the bit.
Page 628 UART Registers content of receive shift register , however, is lost as soon as the overrun occurs. The bit is sticky and can be cleared by W1C operations. UART Line Status Registers (UARTx_LSR) 15 14 13 12 11 10 For memory- Reset = 0x0060 mapped addresses,...
Page 629 UART Port Controllers (framing error) bit indicates that the first stop bit is sampled. The bit is updated simultaneously with the bit, that is, by the time the first stop bit is received or when data is loaded from the receive FIFO to register.
Page 630: Uartx_Msr Registers
UART Registers UARTx_MSR Registers The modem status ( ) registers, shown in Figure 15-11, contains UARTx_MSR current states of the UART’s external pin and current status of UARTxCTS the UART's internal receive buffers. UART Modem Status Registers (UARTx_MSR) 15 14 13 12 11 10 For memory- Reset = 0x0000 mapped...
Page 631: Uartx_Thr Registers
UART Port Controllers bit is a sticky bit that is set high when transitions from SCTS UARTxCTS 0 to 1, and is cleared by software with a W1C operation. The bit can SCTS trigger a line status interrupt if enabled by the bit in the EDSSI UARTx_IER_...
Page 632: Uartx_Rbr Registers
UART Registers UART Transmit Holding Registers (UARTx_THR) 15 14 13 12 11 10 For memory- Reset = 0x0000 mapped addresses, Table 15-9. Transmit Hold[7:0] Figure 15-12. UART Transmit Holding Registers Table 15-9. UART Transmit Holding Register Memory-Mapped Addresses Register Name Memory-Mapped Address UART0_THR 0xFFC0 0428...
Page 633 UART Port Controllers Table 15-10. UART Receive Buffer Register Memory-Mapped Addresses Register Name Memory-Mapped Address UART0_RBR 0xFFC0 042C UART1_RBR 0xFFC0 202C UARTx_IER_SET and UARTx_IER_CLEAR Registers The interrupt enable register is not implemented as a data register. Instead it is controlled by the register pair.
Page 634 UART Registers UART Interrupt Enable Set Registers (UARTx_IER_SET) 15 14 13 12 11 10 For memory- Reset = 0x0000 mapped addresses, Table 15-11. ERBFI (Enable Receive Buf- fer Full Interrupt) ERFCI (Enable Receive FIFO Count Interrupt) 0 - No interrupt 0 - No interrupt 1 - Generate RX interrupt if 1 - Generate status interrupt if RFCS...
Page 635 UART Port Controllers UART Interrupt Enable Clear Registers (UARTx_IER_CLEAR) 15 14 13 12 11 10 For memory- Reset = 0x0000 mapped addresses, Table 15-12. ERBFI (Enable Receive Buf- fer Full Interrupt) ERFCI (Enable Receive FIFO Count Interrupt) 0 - No interrupt 0 - No interrupt 1 - Generate RX interrupt if 1 - Generate status interrupt if RFCS...
Page 636 UART Registers bit enables interrupt generation on an independent interrupt ELSI channel when any of the following conditions are raised by the respective bit in the register: UARTx_LSR • Receive overrun error ( • Receive parity error ( • Receive framing error ( •...
Page 637: Uartx_Dll And Uartx_Dlh Registers
UART Port Controllers a STOP mode DMA. Thus, the normal completion interrupt is sup- pressed. Rather, the event is signalled through the DMA controller TEMT and triggers the DMA interrupt. If both, are set, two DI_EN ETDPTI interrupts are requested at the end of a STOP mode DMA. ...
Page 638: Uartx_Scr Registers
UART Registers Table 15-13. UART Divisor Latch Low Byte Register Memory-Mapped Addresses Register Name Memory-Mapped Address UART0_DLL 0xFFC0 0400 UART1_DLL 0xFFC0 2000 Table 15-14. UART Divisor Latch High Byte Register Memory-Mapped Addresses Register Name Memory-Mapped Address UART0_DLH 0xFFC0 0404 UART1_DLH 0xFFC0 2004 ...
Page 639: Uartx_Gctl Registers
UART Port Controllers Table 15-15. UART Scratch Register Memory-Mapped Addresses Register Name Memory-Mapped Address UART0_SCR 0xFFC0 041C UART1_SCR 0xFFC0 201C UARTx_GCTL Registers The global control ( ) registers, shown in Figure 15-18, contain UARTx_GCTL the enable bit for internal UART clocks and for the IrDA mode of opera- tion of the UARTs.
Page 640: Programming Examples
Programming Examples Table 15-16. UART Global Control Register Memory-Mapped Addresses Register Name Memory-Mapped Address UART0_GCTL 0xFFC0 0408 UART1_GCTL 0xFFC0 2008 bit enables the UART clocks. It also resets the state machine and UCEN control registers when cleared. Note that the bit was not present in UCEN previous UART implementations.
Page 641 UART Port Controllers Listing 15-1. UART Initialization /************************************************************** * Configures UART in 8 data bits, no parity, 1 stop bit mode. * Input parameters: r0 holds divisor latch value to be written into DLH:DLL registers. p0 contains the UARTx_GCTL register address * Return values: none *************************************************************/...
Page 642 Programming Examples The subroutine in Listing 15-2 performs autobaud detection similarly to UART boot. Listing 15-2. UART Autobaud Detection Subroutine /*************************************************************** * Assuming 8 data bits, this functions expects a '@' (ASCII 0x40) character on the UARTx RX pin. A Timer performs the autobaud detection. Input parameters: p0 contains the UARTx_GCTL register address p1 contains the TIMERx_CONFIG register address...
Page 643 UART Port Controllers [p5 + TIMER_STATUS - TIMER_STATUS] = r6; /* clear pending latches */ /* period capture, falling edge to falling edge */ r7 = TIN_SEL | IRQ_ENA | PERIOD_CNT | WDTH_CAP (z); w[p1 + TIMER0_CONFIG - TIMER0_CONFIG] = r7; w[p5+TIMER_ENABLE-TIMER_STATUS] = r5;...
Page 644 Programming Examples The parent routine in Listing 15-3 performs autobaud detection using UART0 TIMER2 Listing 15-3. UART Autobaud Detection Parent Routine p0.l = lo(PORTG_FER); /* function enable on UART0 pins PG12 and PG13 */ p0.h = hi(PORTG_FER); /* by default PORTG_MUX register is all set */ r0 = PG12 | PG13 (z) w[p0] = r0;...
Page 645 UART Port Controllers CC = bittst(r7, bitpos(THRE)); if !CC jump uart_putc.wait; w[p0+UART0_THR-UART0_GCTL] = r0; /* write initiates transfer r7 = [sp++]; rts; uart_putc.end: Use the routine shown in Listing 15-5 to transmit a C-style string that is terminated by a null character. Listing 15-5.
Page 646 Programming Examples Note that polling the register for transmit purposes does not UART0_LSR cause side effects on receive status bits as on former implementations. In non-DMA interrupt operation, the three UART interrupt request lines may or may not be ORed together in the SIC controller or by the EGLSI control bit.
Page 647 UART Port Controllers ssync; r7 = [sp++]; astat = [sp++]; rti; isr_uart_tx.end: isr_uart_error: [--sp] = astat; [--sp] = (r7:6); r7 = w[p0+UART0_LSR-UART0_GCTL] (z); r6 = OE | BI | FE | PE (z); w[p0+UART0_LSR-UART0_GCTL] = r6; /* do something with the error */ (r7:6) = [sp++];...
Page 648 Programming Examples r0 = [p1 + IMASK - IMASK]; /* unmask interrupt in CEC */ bitset(r0, bitpos(EVT_IVG10)); [p1] = r0; p1.l = lo(SIC_IMASK0); p1.h = hi(SIC_IMASK0); /* unmask interrupt in SIC */ r0.l = 0x8000; r0.h = 0x0000; [p1] = r0; [--sp] = reti;...
Page 649 UART Port Controllers p1.h=hi(sWorld); call uart_puts; forever: jump forever; isr_uart_tx: [--sp] = astat; [--sp] = r7; r7 = DMA_DONE (z); /* W1C interrupt request */ w[p5+DMA7_IRQ_STATUS-DMA7_CONFIG] = r7; r7 = ETBEI (z); w[p0+UART0_IER_CLEAR-UART0_GCTL] = r7; ssync; r7 = [sp++]; astat = [sp++]; rti;...
Page 650 Programming Examples 15-56 ADSP-BF50x Blackfin Processor Hardware Reference...
Page 651: Two-Wire Interface Controller
Specific Information for the ADSP-BF50x For details regarding the number of TWIs for the ADSP-BF50x product, refer to ADSP-BF504, ADSP-BF504F, ADSP-BF506F Embedded Processor Data Sheet. For TWI interrupt vector assignments, refer to Table 4-3 on page 4-19 Chapter 4, “System...
Page 652: Overview
Overview Overview The TWI controller allows a device to interface to an inter IC bus as spec- ified by the Philips I C Bus Specification version 2.1 dated January 2000. The TWI is fully compatible with the widely used I C bus standard.
Page 653: Interface Overview
Two-Wire Interface Controller Interface Overview Figure 16-1 provides a block diagram of the TWI controller. The interface is essentially a shift register that serially transmits and receives data bits, one bit at a time at the rate, to and from other TWI devices. The signal synchronizes the shifting and sampling of the data on the serial data pin.
Page 654: Serial Clock Signal (Scl)
Interface Overview Serial Clock Signal (SCL) In slave mode this signal is an input and an external master is responsible for providing the clock. In master mode the TWI controller must set this signal to the desired fre- quency. The TWI controller supports the standard mode of operation (up to 100 KHz) or fast mode (up to 400 KHz).
Page 655: Twi Pins
Two-Wire Interface Controller TWI Pins Table 16-1 shows the pins for the TWI. Two bidirectional pins externally interface the TWI controller to the I C bus. The interface is simple and no other external connections or logic are required. Table 16-1. TWI Pins Description In/Out TWI serial data, high impedance reset value.
Page 656: Description Of Operation
Description of Operation The prescaler block must be programmed to generate a 10 MHz time ref- erence relative to the system clock. This time base is used for filtering of data and timing events specified by the electrical data sheet (See the Phil- ips Specification), as well as for clock generation.
Page 657: Clock Generation And Synchronization
Two-Wire Interface Controller MADDR[6:0] MDIR XMITDATA8[7:0] S = START P = STOP ACK = ACKNOWLEDGE Figure 16-3. Data Transfer With Bit Illustration Clock Generation and Synchronization The TWI controller implementation only issues a clock during master mode operation and only at the time a transfer has been initiated. If arbi- tration for the bus is lost, the serial clock output immediately three-states.
Page 658: Bus Arbitration
Description of Operation Bus Arbitration The TWI controller initiates a master mode transmission ( ) only when the bus is idle. If the bus is idle and two masters initiate a transfer, arbitra- tion for the bus begins. This is shown in Figure 16-5.
Page 659 Two-Wire Interface Controller SCL (BUS) SDA (BUS) STOP START Figure 16-6. TWI Start and Stop Conditions The TWI controller’s special case start and stop conditions include: • TWI controller addressed as a slave-receiver If the master asserts a stop condition during the data phase of a transfer, the TWI controller concludes the transfer ( SCOMP •...
Page 660: General Call Support
Description of Operation General Call Support The TWI controller always decodes and acknowledges a general call address if it is enabled as a slave ( ) and if general call is enabled ( general call addressing (0x00) is indicated by the bit being set and GCALL by nature of the transfer the TWI controller is a slave-receiver.
Page 661: Functional Description
Two-Wire Interface Controller Functional Description The following sections describe the functional operation of the TWI. General Setup General setup refers to register writes that are required for both slave mode operation and master mode operation. General setup should be per- formed before either the master or slave enable bits are set.
Page 662: Master Mode Clock Setup
Functional Description 3. Program . Enable bits are associated with the desired TWI_INT_MASK interrupt sources. As an example, programming the value 0x000F results in an interrupt output to the processor in the event that a valid address match is detected, a valid slave transfer completes, a slave transfer has an error, a subsequent transfer has begun yet the previous transfer has not been serviced.
Page 663: Master Mode Transmit
Two-Wire Interface Controller Master Mode Transmit Follow these programming steps for a single master mode transmit: 1. Program . This defines the address transmitted TWI_MASTER_ADDR during the address phase of the transfer. 2. Program . This is the initial data TWI_XMT_DATA8 TWI_XMT_DATA16 transmitted.
Page 664: Master Mode Receive
Functional Description Table 16-3. Master Mode Transmit Setup Interaction (Cont’d) TWI Controller Master Processor Interrupt: MCOMP – Master transfer com- Acknowledge: Clear interrupt source bits. plete. Master Mode Receive Follow these programming steps for a single master mode receive: 1. Program .
Page 665: Repeated Start Condition
Two-Wire Interface Controller Table 16-4 shows what the interaction between the TWI controller and the processor might look like using this example. Table 16-4. Master Mode Receive Setup Interaction TWI Controller Master Processor Interrupt: RCVFULL – Receive buffer is full. Read receive FIFO buffer.
Page 666 Functional Description The following tasks are performed at each interrupt. • interrupt XMTSERV This interrupt was generated due to a FIFO access. Since this is the last byte of this transfer, indicates the transmit FIFO FIFO_STATUS is empty. When read, would be zero.
Page 667: Receive/Transmit Repeated Start Sequence
Two-Wire Interface Controller Receive/Transmit Repeated Start Sequence Figure 16-8 illustrates a repeated start data receive followed by a data transmit sequence. 7-BIT ADDRESS 8-BIT DATA NACK 7-BIT ADDRESS 8-BIT DATA XMTSERV INTERRUPT RCVSERV INTERRUPT MCOMP INTERRUPT MCOMP INTERRUPT SHADING INDICATES SLAVE HAS THE BUS Figure 16-8.
Page 668: Clock Stretching
Functional Description  There is no timing constraint to meet the above conditions—the user can program the bits as required. Refer to “Clock Stretching During Repeated Start Condition” on page 16-21 for more on how the controller stretches the clock during repeated start transfers. Clock Stretching Clock stretching is an added functionality of the TWI controller in master mode operation.
Page 669 Two-Wire Interface Controller ACK WITH ADDRESS DATA DATA DATA STRETCH XMTSTAT[1:0] TWI_XMT_DATA IS READ AT THIS TIME AND CLOCK STRETCHING IS RELEASED. ACKNOWLEDGE WITH STRETCH ACKNOWLEDGE "STRETCH" BEGINS SOON AFTER SCL FALL. Figure 16-9. Clock Stretching During FIFO Underflow Table 16-5. FIFO Underflow Case TWI Controller Processor Interrupt: XMTSERV –...
Page 670: Clock Stretching During Fifo Overflow
Functional Description Clock Stretching During FIFO Overflow During a master mode receive, an interrupt is generated at the instant the receive FIFO becomes full. It is during the acknowledge phase of this received byte that clock stretching begins. No attempt is made to initiate the reception of an additional byte.
Page 671: Clock Stretching During Repeated Start Condition
Two-Wire Interface Controller Table 16-6. FIFO Overflow Case TWI Controller Processor Interrupt: RCVSERV – Receive FIFO buffer is Acknowledge: Clear interrupt source bits. full. Read receive FIFO buffer. Interrupt: MCOMP – Master receive complete. Acknowledge: Clear interrupt source bits. Clock Stretching During Repeated Start Condition The repeated start feature in I C protocol requires transitioning between two subsequent transfers.
Page 672 Functional Description MCOMP IS SET AT THIS TIME INDICATING INITIAL TRANSFER HAS COMPLETED. RSTART/ ADDRESS DATA ADDRESS DATA STRETCH DCNT[7:0] 0x7F 0x80 0x01 0x00 MDIR (DIRECTION) AND DCNT ARE WRITTEN AT THIS TIME. CLOCK STRETCHING IS RELEASED. REPEATED START WITH STRETCH REPEATED START "STRETCH"...
Page 673: Programming Model
Two-Wire Interface Controller Programming Model Figure 16-12 Figure 16-13 illustrate the programming model for the TWI. WRITE TO TWI_CONTROL TO SET PRESCALE AND ENABLE THE TWI WRITE TO TWI_SLAVE_ADDR WRITE TO TWI_XMT_DATA REGISTER TO PRE-LOAD THE TX FIFO WRITE TO TWI_FIFO_CTL TO SELECT WHETHER 1 OR 2 BYTES GENERATE INTERRUPTS WRITE TO TWI_INT_MASK TO UNMASK TWI EVENTS TO GENERATE INTERRUPTS...
Page 674 Programming Model WRITE TO TWI_CONTROL TO SET PRESCALE AND ENABLE THE TWI WRITE TO TWI_CLK_DIV WRITE TO TWI_MASTER_ADDR WITH THE ADDRESS OF THE TARGETED DEVICE WRITE TO TWI_FIFO_CTL TO SELECT WHETHER 1 OR 2 BYTES GENERATE INTERRUPTS WRITE TO TWI_INT_MASK TO UNMASK TWI EVENTS TO GENERATE INTERRUPTS WRITE TWI_MASTER_CTL WITH COUNT, WRITE TWI_MASTER_CTL WITH COUNT,...
Page 675: Register Descriptions
Two-Wire Interface Controller Register Descriptions The TWI controller has 16 registers described in the following sections. Figure 16-14 through Figure 16-31 on page 16-49 illustrate the registers. TWI CONTROL Register (TWI_CONTROL) register is used to enable the TWI module as well as to TWI_CONTROL establish a relationship between the system clock ( ) and the TWI con-...
Page 676: Scl Clock Divider Register (Twi_Clkdiv)
Register Descriptions TWI Control Register (TWI_CONTROL) 15 14 13 12 11 10 Reset = 0x0000 SCCB (SCCB Compatibility) PRESCALE[6:0] 0 - Master transfers are not SCCB (SCLK Prescale Value) compatible 1 - Master transfers are SCCB compati- ble. All slave-asserted acknowledgement bits are ignored by this master.
Page 677: Twi Slave Mode Control Register (Twi_Slave_Ctl)
Two-Wire Interface Controller low period begins, assuming a single master. It is represented as an 8-bit binary value. field of the register specifies the number of inter- CLKLOW TWI_CLKDIV nal time reference periods the serial clock ( ) is held low. It is represented as an 8-bit binary value.
Page 678 Register Descriptions Additional information for the register bits includes: TWI_SLAVE_CTL • General call enable ( General call address detection is available only when slave mode is enabled. [0] General call address matching is not enabled. [1] General call address matching is enabled. A general call slave receive transfer is accepted.
Page 679: Twi Slave Mode Address Register (Twi_Slave_Addr)
Two-Wire Interface Controller TWI Slave Mode Address Register (TWI_SLAVE_ADDR) register holds the slave mode address, which is the TWI_SLAVE_ADDR valid address that the slave-enabled TWI controller responds to. The TWI controller compares this value with the received address during the addressing phase of a transfer.
Page 680 Register Descriptions During and at the conclusion of register slave mode transfers, the register holds information on the current transfer. Gener- TWI_SLAVE_STAT ally slave mode status bits are not associated with the generation of interrupts. Master mode operation does not affect slave mode status bits. •...
Page 681: Twi Master Mode Control Register (Twi_Master_Ctl)
Two-Wire Interface Controller TWI Master Mode Control Register (TWI_MASTER_CTL) register controls the logic associated with master TWI_MASTER_CTL mode operation. Bits in this register do not affect slave mode operation and should not be modified to control slave mode functionality. TWI Master Mode Control Register (TWI_MASTER_CTL) 15 14 13 12 11 10 Reset = 0x0000 MEN (Master Mode Enable)
Page 682 Register Descriptions • Serial data (SDA) override ( SDAOVR This bit can be used when direct control of the serial data line is required. Normal master and slave mode operation should not require override operation. [0] Normal serial data operation under the control of the transmit shift register and acknowledge logic.
Page 683 Two-Wire Interface Controller • Issue stop condition ( STOP [0] Normal transfer operation. [1] The transfer concludes as soon as possible avoiding any error conditions (as if data transfer count had been reached) and at that time the TWI interrupt mask register ( ) is updated TWI_INT_MASK along with any associated status bits.
Page 684: Twi Master Mode Address Register (Twi_Master_Addr)
Register Descriptions TWI Master Mode Address Register (TWI_MASTER_ADDR) During the addressing phase of a transfer, the TWI controller, with its master enabled, transmits the contents of the register. TWI_MASTER_ADDR When programming this register, omit the read/write bit. That is, only the upper 7 bits that make up the slave address should be written to this regis- ter.
Page 685: Twi Master Mode Status Register (Twi_Master_Stat)
Two-Wire Interface Controller TWI Master Mode Status Register (TWI_MASTER_STAT) TWI Master Mode Status Register (TWI_MASTER_STAT) 15 14 13 12 11 10 Reset = 0x0000 MPROG (Master Transfer BUSBUSY (Bus Busy) - RO in Progress) - RO SCLSEN (Serial Clock Sense) - RO LOSTARB (Lost Arbitration) - SDASEN (Serial Data Sense) - RO BUFWRERR (Buffer Write Error) - W1C...
Page 686 Register Descriptions • Bus busy ( BUSBUSY Indicates whether the bus is currently busy or free. This indication is not limited to only this device but is for all devices. Upon a start condition, the setting of the register value is delayed due to the input filtering.
Page 687 Two-Wire Interface Controller [1] An active “zero” is currently being sensed on the serial data line. The source of the active driver is not known and can be internal or external. • Buffer write error ( BUFWRERR [0] The current master receive has not detected a receive buffer write error.
Page 688: Twi Fifo Control Register (Twi_Fifo_Ctl)
Register Descriptions • Lost arbitration ( LOSTARB [0] The current transfer has not lost arbitration with another master. [1] The current transfer was aborted due to the loss of arbitration with another master. This bit is W1C. • Master transfer in progress ( MPROG [0] Currently no transfer is taking place.
Page 689 Two-Wire Interface Controller Additional information for the register bits includes: TWI_FIFO_CTL • Receive buffer interrupt length ( RCVINTLEN This bit determines the rate at which receive buffer interrupts are to be generated. Interrupts may be generated with each byte received or after two bytes are received. [0] An interrupt ( ) is set when indicates one or...
Page 690: Twi Fifo Status Register (Twi_Fifo_Stat)
Register Descriptions • Transmit buffer flush ( XMTFLUSH [0] Normal operation of the transmit buffer and its status bits. [1] Flush the contents of the transmit buffer and update the status bit to indicate the buffer is empty. This state is held XMTSTAT until this bit is cleared.
Page 691 Two-Wire Interface Controller • Receive FIFO status ( RCVSTAT[1:0] field is read only. It indicates the number of valid data RCVSTAT bytes in the receive FIFO buffer. The status is updated with each FIFO buffer read using the peripheral data bus or write access by the receive shift register.
Page 692: Twi Interrupt Mask Register (Twi_Int_Mask)
Register Descriptions TWI Interrupt Mask Register (TWI_INT_MASK) register enables interrupt sources to assert the interrupt TWI_INT_MASK output. Each mask bit corresponds with one interrupt source bit in the register. Reading and writing the register TWI_INT_STAT TWI_INT_MASK does not affect the contents of the register.
Page 693: Twi Interrupt Status Register (Twi_Int_Stat)
Two-Wire Interface Controller TWI Interrupt Status Register (TWI_INT_STAT) TWI Interrupt Status Register (TWI_INT_STAT) All bits are sticky and W1C. 15 14 13 12 11 10 Reset = 0x0000 SINIT (Slave Transfer RCVSERV (Receive FIFO Service) Initiated) XMTSERV (Transmit FIFO Service) SCOMP (Slave Transfer MERR (Master Transfer Error) Complete)
Page 694 Register Descriptions • Transmit FIFO service ( XMTSERV in the register is 0, this bit is set each XMTINTLEN TWI_FIFO_CTL time the field in the register is updated to XMTSTAT TWI_FIFO_STAT either 01 or 00. If is 1, this bit is set each time XMTINTLEN XMTSTAT is updated to 00.
Page 695 Two-Wire Interface Controller • Slave transfer error ( SERR [0] No errors have been detected. [1] A slave error has occurred. A restart or stop condition has occurred during the data receive phase of a transfer. • Slave transfer complete ( SCOMP [0] The completion of a transfer has not been detected.
Page 696: Twi Fifo Transmit Data Single Byte
Register Descriptions TWI FIFO Transmit Data Single Byte Register (TWI_XMT_DATA8) register holds an 8-bit data value written into the TWI_XMT_DATA8 FIFO buffer. Transmit data is entered into the corresponding transmit buffer in a first-in first-out order. For 16-bit PAB writes, a write access to adds only one transmit data byte to the FIFO buffer.
Page 697: Twi Fifo Transmit Data Double Byte
Two-Wire Interface Controller TWI FIFO Transmit Data Double Byte Register (TWI_XMT_DATA16) register holds a 16-bit data value written into the TWI_XMT_DATA16 FIFO buffer. To reduce interrupt output rates and peripheral bus access times, a double byte transfer data access can be performed. Two data bytes can be written, effectively filling the transmit FIFO buffer with a single access.
Page 698: Twi Fifo Receive Data Single Byte
Register Descriptions TWI FIFO Receive Data Single Byte Register (TWI_RCV_DATA8) register holds an 8-bit data value read from the FIFO TWI_RCV_DATA8 buffer. Receive data is read from the corresponding receive buffer in a first-in first-out order. Although peripheral bus reads are 16 bits, a read access to will access only one transmit data byte from the TWI_RCV_DATA8...
Page 699 Two-Wire Interface Controller performed while the FIFO buffer is not full, the read data is unknown and the existing FIFO buffer data and its status remains unchanged. RECEIVE DATA REGISTER TRANSMISSION LINE Figure 16-30. Receive Little Endian Byte Order TWI FIFO Receive Data Double Byte Register (TWI_RCV_DATA16) All bits are WO.
Page 700: Programming Examples
Programming Examples Programming Examples The following sections include programming examples for general setup, slave mode, and master mode, as well as guidance for repeated start conditions. Master Mode Setup Listing 16-1 shows how to initiate polled receive and transmit transfers in master mode.
Page 701 Two-Wire Interface Controller Prescale = 10 (0xA) for an SCLK = 100 MHz (CLKIN = 50MHz) Prescale = SCLK / 10 MHz P1 points to the base of the system MMRs ***********************************************************/ R1 = TWI_ENA | 0xA (z); W[P1 + LO(TWI_CONTROL)] = R1; /*********************************************************** Set CLKDIV: For example, for an SCL of 400 KHz (period = 1/400 KHz = 2500 ns)
Page 702 Programming Examples R6 = R6 >> 1; TWI_INIT.END: W[P1 + LO(TWI_MASTER_ADDR)] = R6; /******************** END OF TWI INIT **********************/ /*********************************************************** Starting the Read transfer Program the Master Control register with: 1. the number of bytes to transfer: TWICount(x) 2. Repeated Start (RESTART): optional 3.
Page 703 Two-Wire Interface Controller check that master transfer has completed MCOMP is set when Count reaches zero ***********************************************************/ M_COMP: R1 = W[P1 + LO(TWI_INT_STAT)](z); CC = BITTST (R1, bitpos(MCOMP)); if ! CC jump M_COMP; M_COMP.END: W[P1 + LO(TWI_INT_STAT)] = R1; /* load the pointer with the address of the transmit buffer */ P2.H = TX_file;...
Page 704 Programming Examples SSYNC; /*********************************************************** loop to write data to a TWI slave device P3 times ***********************************************************/ P3 = length(TX_file); LSETUP (Loop_Start1, Loop_End1) LC0 = P3; Loop_Start1: /******************************************************* check that there's at least one byte location empty in the tx fifo *******************************************************/ XMTSERV_Status: R1 = W[P1 + LO(TWI_INT_STAT)](z);...
Page 705: Slave Mode Setup
Two-Wire Interface Controller idle; _main.end: Slave Mode Setup Listing 16-2 shows how to configure the slave for interrupt based trans- fers. The interrupts are serviced in the subroutine shown in _TWI_ISR Listing 16-3. Listing 16-2. Slave Mode Setup #include <defBF527.h> /*BF527 is used here as an example—change as appropriate.*/ #include "startup.h"...
Page 706 Programming Examples /*********************************************************** Enable the TWI controller and set the Prescale value Prescale = 10 (0xA) for an SCLK = 100 MHz (CLKIN = 50MHz) Prescale = SCLK / 10 MHz P1 points to the base of the system MMRs P0 points to the base of the core MMRs ***********************************************************/ R1 = TWI_ENA | 0xA (z);...
Page 707 Two-Wire Interface Controller W[P1 + LO(TWI_FIFO_CTL)] = R1; /*********************************************************** enable these signals to generate a TWI interrupt ***********************************************************/ R1 = RCVSERV | XMTSERV | SOVF | SERR | SCOMP | SINIT (z); W[P1 + LO(TWI_INT_MASK)] = R1; /*********************************************************** Enable the TWI Slave Program the Slave Control register with: 1.
Page 708 Programming Examples /*********************************************************** ENABLE TWI generate to interrupts at the system level ***********************************************************/ R1 = [P1 + LO(SIC_IMASK)]; BITSET(R1,BITPOS(IRQ_TWI)); [P1 + LO(SIC_IMASK)] = R1; /*********************************************************** ENABLE TWI to generate interrupts at the core level ***********************************************************/ R1 = [P0 + LO(IMASK)]; BITSET(R1,BITPOS(EVT_IVG10));...
Page 709 Two-Wire Interface Controller .GLOBAL _TWI_ISR; .section L1_code; _TWI_ISR: /*********************************************************** read the source of the interrupt ***********************************************************/ R1 = W[P1 + LO(TWI_INT_STAT)](z); /*********************************************************** Slave Transfer Initiated ***********************************************************/ CC = BITTST(R1, BITPOS(SINIT)); if ! CC JUMP RECEIVE; R0 = SINIT (Z); W[P1 + LO(TWI_INT_STAT)] = R0; /* clear interrupt source bit */ ssync;...
Page 710 Programming Examples ***********************************************************/ TRANSMIT: CC = BITTST(R1, BITPOS(XMTSERV)); if ! CC JUMP SlaveError; R0 = B[P4++](Z); W[P1 + LO(TWI_XMT_DATA8)] = R0; R0 = XMTSERV(Z); W[P1 + LO(TWI_INT_STAT)] = R0; /* clear interrupt source bit */ ssync; JUMP _TWI_ISR.END; /* exit */ /*********************************************************** slave transfer error ***********************************************************/...
Page 711: Electrical Specifications
Two-Wire Interface Controller slave transfer complete ***********************************************************/ SlaveTransferComplete: CC = BITTST(R1, BITPOS(SCOMP)); if !CC JUMP _TWI_ISR.END; R0 = SCOMP(Z); W[P1 + LO(TWI_INT_STAT)] = R0; /* clear interrupt source bit */ ssync; /* Transfer complete read receive FIFO buffer and set/clear sema- phores etc..
Page 712 Unique Information for the ADSP-BF50x Processor 16-62 ADSP-BF50x Blackfin Processor Hardware Reference...
Page 713: 17 Can Module
17 CAN MODULE This chapter describes the Controller Area Network (CAN) module. Fol- lowing an overview and a list of key features is a description of operation. The chapter concludes with a programming model, consolidated register definitions, and programming examples. Familiarity with the CAN stan- dard is assumed.
Page 714: Interface Overview
Interface Overview • 32 mailboxes (8 transmit, 8 receive, 16 configurable) • Dedicated acceptance mask for each mailbox • Data filtering (first 2 bytes) can be used for acceptance filtering (DeviceNet™ mode) • Error status and warning registers • Universal counter module •...
Page 715 CAN Module BLACKFIN SIC CONTROLLER CANx INTERRUPT GLOBAL INTERRUPT FLAG GLOBAL INTERRUPT MASK GLOBAL INTERRUPT STATUS ERROR COUNTERS ERROR STATUS ERROR WARNING MAILBOX INTERRUPT MASK 1 MAILBOX INTERRUPT TRANSMIT 1 MAILBOX INTERRUPT MASK 2 MAILBOX INTERRUPT RECEIVE 1 MAILBOX INTERRUPT TRANSMIT 2 OVERWRITE PROTECTION/SINGLE SHOT 1 AILBOX INTERRUPT RECEIVE 2 COUNTER...
Page 716: Can Mailbox Area
Interface Overview signals can be found on GPIO Port G, pins CANRX CANTX . CAN data is defined to be either dominant (logic 0) or recessive (logic 1). The default state of the output is recessive. CANTX pin ( input pin) is also internally routed to the alternated CANRX capture input of GP timer 5.
Page 717 CAN Module  Do not write to the identifier of a message object while the mailbox is enabled for the CAN module (the corresponding bit in CAN_MCx is set). CAN_MB00_DATA0 WORD0 BYTE 6 BYTE 7 CAN_MB00_DATA1 WORD1 BYTE 4 BYTE 5 CAN_MB00_DATA2 WORD2 BYTE 2...
Page 718: Can Mailbox Control
Interface Overview The final registers in the mailbox area are the acceptance mask registers ). The acceptance mask is enabled when the CAN_AMxxH CAN_AMxxL bit is set in the register. If the “filtering on data field” CAN_MBxx_ID1 option is enabled ( in the register and in the...
Page 719: Can Protocol Basics
CAN Module • (transmit acknowledge registers) CAN_TA1 CAN_TA2 • (abort acknowledge registers) CAN_AA1 CAN_AA2 • (transmit request set registers) CAN_TRS1 CAN_TRS2 • (transmit request reset registers) CAN_TRR1 CAN_TRR2 • (receive message pending registers) CAN_RMP1 CAN_RMP2 • (receive message lost registers) CAN_RML1 CAN_RML2 •...
Page 720 Interface Overview pin is always high. If two CAN nodes transmit at the same time, dominant bits overwrite recessive bits. The CAN protocol defines that all nodes trying to send a message on the CAN bus attempt to send a frame once the CAN bus becomes available. The start of frame indicator ( ) signals the beginning of a new frame.
Page 721: Can Operation
CAN Module  Due to the inherent nature of the CAN protocol, a dominant bit in field wins arbitration against a remote frame request ) for the same message ID, thereby defining a remote request to be lower priority than a data frame. The next field of interest is the .
Page 722: Bit Timing
CAN Operation Bit Timing The CAN controller does not have a dedicated clock. Instead, the CAN clock is derived from the system clock ( ) based on a configurable SCLK number of time quanta. The Time Quantum (TQ) is derived from the formula , where is the 10-bit...
Page 723 CAN Module needed to complete the bit time. Often, best sample reliability is achieved with sample points in the high 80% range of the bit time. Never use sam- ple points lower than 50%. Thus, should always be greater than or TSEG1 equal to TSEG2...
Page 724: Transmit Operation
CAN Operation resulting value is generated by a majority decision of the three sample val- ues. Always keep the bit cleared if the value is less than 4. Do not modify the registers during normal oper- CAN_CLOCK CAN_TIMING ation. Always enter configuration mode first. Writes to these registers have no effect if not in configuration or debug mode.
Page 725: Retransmission
CAN Module bit in the transmit acknowledge register ( ) is set. If the CAN_TAx transmission was aborted due to lost arbitration or a CAN error, the corre- sponding bit in the abort acknowledge register ( ) is set. A CAN_AAx requested transmission can also be manually aborted by setting the corre- sponding...
Page 726: Single Shot Transmission
CAN Operation AT LEAST 1 BIT SET IN CAN_TRSx REGISTERS STARTING WITH MAILBOX 31, FIND HIGHEST SET TRSn BIT PLACE MESSAGE n IN TEMPORARY TRANSMIT BUFFER MESSAGE ABORTED? CLEAR TRSn CLEAR TRSn AND REPORT AND REPORT TRANSMIT ABORT ERROR SUCCESSFUL EXIT EXIT Figure 17-8.
Page 727: Auto-Transmission
CAN Module the CAN bus line. Thus, there is no further attempt to transmit the mes- sage again if the initial try failed, and the abort error is reported ( CAN_AAx Auto-Transmission In auto-transmit mode, the message in mailbox 11 can be sent periodically using the universal counter.
Page 728 CAN Operation The message identifier of the received message, along with the identifier extension ( ) and remote transmission request ( ) bits, are compared against each mailbox’s register settings. If the bit is not set, a match is signalled only if , and all identifier bits are exact.
Page 729 CAN Module Figure 17-9 illustrates the decision tree of the receive logic when process- ing the individual mailboxes. FROM MESSAGE RECEIVER/PREVIOUS MAILBOX MAILBOX NEXT MAILBOX ENABLED? COMPARE COMPARE ALL UNMASKED AME? BITS BITS ONLY NEXT MAILBOX MATCH? TRANSMIT RECEIVE MAILBOX DIRECTION? REMOTE MAILBOX...
Page 730: Data Acceptance Filter
CAN Operation results in the receive message lost interrupt being raised in the global CAN interrupt status register ( ). If , the next mail- RMLIS CAN_GIS OPSSn boxes are checked for another matching identifier. If no match is found, the message is discarded and the next message is checked.
Page 731: Remote Frame Handling
CAN Module Remote Frame Handling Automatic handling of remote frames can be enabled/disabled by setting/ clearing the corresponding bit in the remote frame handling registers ) of a transmit mailbox. CAN_RFHx Remote frames are data frames with no data field and the bit set.
Page 732: Time Stamps
CAN Operation Upon programming the universal counter to watchdog mode (set ), the counter in the register is UCCNF[3:0] CAN_UCCNF CAN_UCCNT loaded with the predefined value contained in the CAN universal counter reload/capture register ( ). This counter then decrements at the CAN_UCRC CAN bit rate.
Page 733: Temporarily Disabling Mailboxes
CAN Module configured as transmit) or the reception of the requested data frame (mail- box configured as receive). The counter can be cleared (set bit to 1) or disabled (set bit to 0) UCRC by writing to the register. The counter can also be loaded with CAN_UCCNF a value by writing to the counter register itself ( CAN_UCCNT...
Page 734: Functional Operation
Functional Operation logic and the data length code of the incoming message is written to the corresponding mailbox. However, the message being requested is not sent until the temporary disable request is cleared ( ). Similarly, all trans- mit requests for temporarily disabled mailboxes are ignored until cleared.
Page 735: Mailbox Interrupts
CAN Module Mailbox Interrupts Each of the 32 mailboxes in the CAN module may generate a receive or transmit interrupt, depending on the mailbox configuration. To enable a mailbox to generate an interrupt, set the corresponding bit in MBIMn CAN_MBIMx If a mailbox is configured as a receive mailbox, the corresponding receive interrupt flag is set ( ) after a received message is...
Page 736 Functional Operation status bits in the global CAN interrupt status register, however, are always set if the corresponding interrupt event occurs, independent of the mask bits. Thus, the interrupt status bits can be used for polling of interrupt events. The global CAN status interrupt output ( ) bit in the global CAN GIRQ interrupt status register is only asserted if a bit in the...
Page 737 CAN Module there is at least one bit in still set, the bit in (and CAN_RMLx CAN_GIS ) is not set again. The internal interrupt source signal is CAN_GIF only active if a new bit in is set. CAN_RMLx • Abort acknowledge interrupt ( AAIM AAIS AAIF...
Page 738: Event Counter
Functional Operation (and ) is reset and the error-passive mode is still CAN_GIS CAN_GIF active, this bit is not set again. If the module leaves the error-pas- sive mode, the bit in (and ) remains set. CAN_GIS CAN_GIF • Error warning receive interrupt ( EWRIM EWRIS EWRIF...
Page 739: Can Warnings And Errors
CAN Module • – Transmission aborted. Counter is incre- UCCNF[3:0] = 0x9 mented every time arbitration is lost or a transmit request is cancelled ( is set). • – Transmission succeeded. Counter is incre- UCCNF[3:0] = 0xA mented every time a message sends without detected errors ( set).
Page 740: Programmable Warning Limits
Functional Operation Programmable Warning Limits It is possible to program the warning level for (error warning trans- EWTIS mit interrupt status) and (error warning receive interrupt status) EWRIS separately by writing to the error warning level error count fields for receive ( ) and transmit ( ) in the CAN error counter warning...
Page 741: Error Frames
CAN Module • CRC error A CRC error occurs whenever a receiver calculates the CRC on the data it received and finds it different than the CRC that was trans- mitted on the bus itself. • Stuff error The CAN specification requires the transmitter to insert an extra stuff bit of opposite value after 5 bits have been transmitted with the same value.
Page 742 Functional Operation Finally, all nodes on the bus have detected an error. Consequently, all of them send 6 dominant and 8 recessive bits to the bus as well. The result- ing error frame consists of two different fields. The first field is given by the superposition of error flags contributed from the different stations, which is a sequence of 6 to 12 dominant bits.
Page 743: Error Levels
CAN Module Because the transmission of an error frame destroys the frame under trans- mission, a faulty node erroneously detecting an error can block the bus. Because of this, there are two node states which determine a node’s right to signal an error—error active and error passive. Error active nodes are those which have an error detection rate below a certain limit.
Page 744 Functional Operation If one of the counters exceeds 255 (that is, when the 8-bit counters over- flow), the CAN module is disconnected from the bus. It goes into bus off mode and the CAN error bus off mode ( ) bit is set in .
Page 745: Debug And Test Modes
CAN Module During the bus off recovery sequence, the configuration mode request bit in the register is set by the internal logic ( ), thus the CAN_CONTROL CAN core module does not automatically come out of the bus off mode. bit cannot be reset until the bus off recovery sequence is finished.
Page 746 Functional Operation /* Set debug flags */ *pCAN_DEBUG &= ~DTO ; *pCAN_DEBUG |= MRB | MAA | DIL ; /* Run test code */ /* Disable debug mode */ *pCAN_DEBUG &= ~CDE ; When the bit is set, it enables writes to the other bits of the CAN_DEBUG register.
Page 747 CAN Module The disable internal loop bit ( ) is used to internally enable the transmit output to be routed back to the receive input. The disable transmit output bit ( ) is used to disable the output CANTX pin. When this bit is set, the pin continuously drives recessive bits.
Page 748 Functional Operation Table 17-4. CAN Test Modes (Cont’d) Functional Description Normal transmission on CAN bus line. Read back. No external acknowledge required. Transmit message and acknowledge are transmitted on CAN bus line. CANRX input is enabled. Normal transmission on CAN bus line.
Page 749: Low Power Features
CAN Module Low Power Features The Blackfin processor provides a low power hibernate state, and the CAN module includes built-in sleep and suspend modes to save power. The behavior of the CAN module in these three modes is described in the following sections.
Page 750: Can Built-In Sleep Mode
Functional Operation CAN Built-In Sleep Mode The next level of power savings can be realized by using the CAN mod- ule’s built-in sleep mode. This mode is entered by setting the sleep mode request ( ) bit in the register. The module enters the sleep CAN_CONTROL mode after the current operation of the CAN bus is finished.
Page 751: Can Register Definitions
CAN Module responds appropriately. Otherwise, the activity on the pin has no CANRX effect on the processor state. To enable this functionality, the voltage control register ( ) must be VR_CTL programmed with the CAN wakeup enable bit set. The typical sequence of events to use the CAN wakeup feature is: 1.
Page 752 CAN Register Definitions Table 17-5. Global CAN Register Mapping (Cont’d) Register Name Function Notes CAN_CLOCK CAN clock register Accessible only in configuration mode CAN_TIMING CAN timing register Accessible only in configuration mode CAN_INTR CAN interrupt register Reserved bits 15:8 and 5:4 must always be written as ‘0’...
Page 753 CAN Module Table 17-7. CAN Mailbox Control Register Mapping Register Name Function Notes CAN_MCx Mailbox configura- Always disable before modifying mailbox area tion registers or direction CAN_MDx Mailbox direction Never change MDn direction when mailbox n registers is enabled. MD[31:24] and MD[7:0] are read only CAN_RMPx Receive message...
Page 754 CAN Register Definitions Table 17-7. CAN Mailbox Control Register Mapping (Cont’d) Register Name Function Notes CAN_MBTIFx Mailbox transmit Can be cleared if mailbox or mailbox interrupt interrupt flag regis- is disabled. Changing direction while MBTIFn ters = 1 results in MBRIFn = 1 and MBTIFn = 0 CAN_MBRIFx Mailbox receive Can be cleared if mailbox or mailbox interrupt...
Page 755: Global Can Registers
CAN Module Global CAN Registers Figure 17-11 through Figure 17-19 show the global CAN registers. CAN_CONTROL Register Master Control Register (CAN_CONTROL) 15 14 13 12 11 10 Reset = 0x0080 0xFFC0 2AA0 SRS (Software Reset) CCR (CAN Configuration Mode Request) 0 - No effect 1 - Reset 0 - Cancelled...
Page 756: Can_Status Register
CAN Register Definitions CAN_STATUS Register Global CAN Status Register (CAN_STATUS) 15 14 13 12 11 10 0xFFC0 2A8C Reset = 0x0000 WT (CAN Transmit Warning REC (Receive Flag) Mode) 0 - TXECNT below limit 0 - Not in receive mode 1 - TXECNT at limit 1 - In receive mode WR (CAN Receive Warning...
Page 757: Can_Debug Register
CAN Module CAN_DEBUG Register CAN Debug Register (CAN_DEBUG) 15 14 13 12 11 10 Reset = 0x0008 0xFFC0 2A88 DEC (Disable Transmit and CDE (CAN Debug Receive Error Counters) Mode Enable) 0 - Enable CAN_CEC transmit 0 - Debug mode disabled and receive error counters 1 - Debug mode enabled 1 - Disable CAN_CEC transmit...
Page 758: Can_Timing Register
CAN Register Definitions CAN_TIMING Register CAN Timing Register (CAN_TIMING) 15 14 13 12 11 10 0xFFC0 2A84 Reset = 0x0000 TSEG1[3:0] (Time Segment 1) SJW[1:0] (Synchronization Jump Width) TSEG2[2:0] (Time Segment 2) SAM (Sampling) Figure 17-15. CAN Timing Register CAN_INTR Register CAN Interrupt Register (CAN_INTR) 15 14 13 12 11 10 0xFFC0 2AA4...
Page 759: Can_Gim Register
CAN Module CAN_GIM Register Global CAN Interrupt Mask Register (CAN_GIM) 15 14 13 12 11 10 0xFFC0 2A98 Reset = 0x0080 EWTIM (Error Warning Transmit ADIM (Access Denied Interrupt Mask) Interrupt Mask) EXTIM (External Trigger Interrupt Mask) EWRIM (Error Warning Receive UCEIM (Universal Counter Exceeded Interrupt Mask) Interrupt Mask)
Page 760: Can_Gif Register
CAN Register Definitions CAN_GIF Register Global CAN Interrupt Flag Register (CAN_GIF) 15 14 13 12 11 10 0xFFC0 2A9C Reset = 0x0000 EWTIF (Error Warning Trans- ADIF (Access Denied Interrupt Flag) mit Interrupt Flag) EXTIF (External Trigger Interrupt Flag) EWRIF (Error Warning UCEIF (Universal Counter Exceeded Receive Interrupt Flag) Interrupt Flag)
Page 761 CAN Module The value of the acceptance mask register does not care when the bit is zero. If is set, only those bits are compared that have the correspond- ing mask bit cleared. A bit position that is one in the mask register does not need to match.
Page 762 CAN Register Definitions Table 17-10. Acceptance Mask Register (H) Memory-Mapped Addresses (Cont’d) Register Name Memory-Mapped Address CAN_AM21H 0xFFC0 2BAC CAN_AM22H 0xFFC0 2BB4 CAN_AM23H 0xFFC0 2BBC CAN_AM24H 0xFFC0 2BC4 CAN_AM25H 0xFFC0 2BCC CAN_AM26H 0xFFC0 2BD4 CAN_AM27H 0xFFC0 2BDC CAN_AM28H 0xFFC0 2BE4 CAN_AM29H 0xFFC0 2BEC CAN_AM30H...
Page 763 CAN Module Table 17-11. Acceptance Mask Register (L) Memory-Mapped Addresses (Cont’d) Register Name Memory-Mapped Address CAN_AM03L 0xFFC0 2B18 CAN_AM04L 0xFFC0 2B20 CAN_AM05L 0xFFC0 2B28 CAN_AM06L 0xFFC0 2B30 CAN_AM07L 0xFFC0 2B38 CAN_AM08L 0xFFC0 2B40 CAN_AM09L 0xFFC0 2B48 CAN_AM10L 0xFFC0 2B50 CAN_AM11L 0xFFC0 2B58 CAN_AM12L 0xFFC0 2B60...
Page 764: Can_Mbxx_Id1 Registers
CAN Register Definitions Table 17-11. Acceptance Mask Register (L) Memory-Mapped Addresses (Cont’d) Register Name Memory-Mapped Address CAN_AM28L 0xFFC0 2BE0 CAN_AM29L 0xFFC0 2BE8 CAN_AM30L 0xFFC0 2BF0 CAN_AM31L 0xFFC0 2BF8 CAN_MBxx_ID1 Registers Mailbox Word 7 Register (CAN_MBxx_ID1) 15 14 13 12 11 10 Reset = 0xXXXX For memory- mapped...
Page 765 CAN Module Table 17-12. Mailbox Word 7 Register Memory-Mapped Addresses (Cont’d) Register Name Memory-Mapped Address CAN_MB07_ID1 0xFFC0 2CFC CAN_MB08_ID1 0xFFC0 2D1C CAN_MB09_ID1 0xFFC0 2D3C CAN_MB10_ID1 0xFFC0 2D5C CAN_MB11_ID1 0xFFC0 2D7C CAN_MB12_ID1 0xFFC0 2D9C CAN_MB13_ID1 0xFFC0 2DBC CAN_MB14_ID1 0xFFC0 2DDC CAN_MB15_ID1 0xFFC0 2DFC CAN_MB16_ID1 0xFFC0 2E1C...
Page 766: Can_Mbxx_Id0 Registers
CAN Register Definitions CAN_MBxx_ID0 Registers Mailbox Word 6 Register (CAN_MBxx_ID0) 15 14 13 12 11 10 Reset = 0xXXXX For memory- mapped addresses, see EXTID[15:0]/DFC[15:0] Table 17-13. (Extended Identifier/Data Field Acceptance Code) Figure 17-23. Mailbox Word 6 Register Table 17-13. Mailbox Word 6 Register Memory-Mapped Addresses Register Name Memory-Mapped Address...
Page 767 CAN Module Table 17-13. Mailbox Word 6 Register Memory-Mapped Addresses (Cont’d) Register Name Memory-Mapped Address CAN_MB16_ID0 0xFFC0 2E18 CAN_MB17_ID0 0xFFC0 2E38 CAN_MB18_ID0 0xFFC0 2E58 CAN_MB19_ID0 0xFFC0 2E78 CAN_MB20_ID0 0xFFC0 2E98 CAN_MB21_ID0 0xFFC0 2EB8 CAN_MB22_ID0 0xFFC0 2ED8 CAN_MB23_ID0 0xFFC0 2EF8 CAN_MB24_ID0 0xFFC0 2F18 CAN_MB25_ID0 0xFFC0 2F38...
Page 768: Can_Mbxx_Timestamp Registers
CAN Register Definitions CAN_MBxx_TIMESTAMP Registers Mailbox Word 5 Register (CAN_MBxx_ID0) 15 14 13 12 11 10 Reset = 0xXXXX For memory- mapped addresses, see EXTID[15:0]/DFC[15:0] Table 17-13. (Extended Identifier/Data Field Acceptance Code) Figure 17-24. Mailbox Word 5 Register Table 17-14. Mailbox Word 5 Register Memory-Mapped Addresses Register Name Memory-Mapped Address...
Page 769 CAN Module Table 17-14. Mailbox Word 5 Register Memory-Mapped Addresses (Cont’d) Register Name Memory-Mapped Address CAN_MB16_TIMESTAMP 0xFFC0 2E14 CAN_MB17_TIMESTAMP 0xFFC0 2E34 CAN_MB18_TIMESTAMP 0xFFC0 2E54 CAN_MB19_TIMESTAMP 0xFFC0 2E74 CAN_MB20_TIMESTAMP 0xFFC0 2E94 CAN_MB21_TIMESTAMP 0xFFC0 2EB4 CAN_MB22_TIMESTAMP 0xFFC0 2ED4 CAN_MB23_TIMESTAMP 0xFFC0 2EF4 CAN_MB24_TIMESTAMP 0xFFC0 2F14 CAN_MB25_TIMESTAMP 0xFFC0 2F34...
Page 770: Can_Mbxx_Length Registers
CAN Register Definitions CAN_MBxx_LENGTH Registers Mailbox Word 4 Register (CAN_MBxx_LENGTH) 15 14 13 12 11 10 Reset = 0xXXXX For memory- mapped addresses, see DLC[3:0] (Data Length Code) Table 17-25. Figure 17-25. Mailbox Word 4 Register Table 17-15. Mailbox Word 4 Register Memory-Mapped Addresses Register Name Memory-Mapped Address...
Page 771: Can_Mbxx_Datax Registers
CAN Module Table 17-15. Mailbox Word 4 Register Memory-Mapped Addresses (Cont’d) Register Name Memory-Mapped Address CAN_MB17_LENGTH 0xFFC0 2E30 CAN_MB18_LENGTH 0xFFC0 2E50 CAN_MB19_LENGTH 0xFFC0 2E70 CAN_MB20_LENGTH 0xFFC0 2E90 CAN_MB21_LENGTH 0xFFC0 2EB0 CAN_MB22_LENGTH 0xFFC0 2ED0 CAN_MB23_LENGTH 0xFFC0 2EF0 CAN_MB24_LENGTH 0xFFC0 2F10 CAN_MB25_LENGTH 0xFFC0 2F30 CAN_MB26_LENGTH 0xFFC0 2F50...
Page 772 CAN Register Definitions Table 17-16. Mailbox Word 3 Register Memory-Mapped Addresses Register Name Memory-Mapped Address CAN_MB00_DATA3 0xFFC0 2C0C CAN_MB01_DATA3 0xFFC0 2C2C CAN_MB02_DATA3 0xFFC0 2C4C CAN_MB03_DATA3 0xFFC0 2C6C CAN_MB04_DATA3 0xFFC0 2C8C CAN_MB05_DATA3 0xFFC0 2CAC CAN_MB06_DATA3 0xFFC0 2CCC CAN_MB07_DATA3 0xFFC0 2CEC CAN_MB08_DATA3 0xFFC0 2D0C CAN_MB09_DATA3 0xFFC0 2D2C...
Page 773 CAN Module Table 17-16. Mailbox Word 3 Register Memory-Mapped Addresses (Cont’d) Register Name Memory-Mapped Address CAN_MB25_DATA3 0xFFC0 2F2C CAN_MB26_DATA3 0xFFC0 2F4C CAN_MB27_DATA3 0xFFC0 2F6C CAN_MB28_DATA3 0xFFC0 2F8C CAN_MB29_DATA3 0xFFC0 2FAC CAN_MB30_DATA3 0xFFC0 2FCC CAN_MB31_DATA3 0xFFC0 2FEC ADSP-BF50x Blackfin Processor Hardware Reference 17-61...
Page 774 CAN Register Definitions Mailbox Word 2 Register (CAN_MBxx_DATA2) 15 14 13 12 11 10 Reset = 0xXXXX For memory- mapped addresses, see Table 17-17. Data Field Byte 2[7:0] Data Field Byte 3[7:0] Figure 17-27. Mailbox Word 2 Register Table 17-17. Mailbox Word 2 Register Memory-Mapped Addresses Register Name Memory-Mapped Address...
Page 775 CAN Module Table 17-17. Mailbox Word 2 Register Memory-Mapped Addresses (Cont’d) Register Name Memory-Mapped Address CAN_MB18_DATA2 0xFFC0 2E48 CAN_MB19_DATA2 0xFFC0 2E68 CAN_MB20_DATA2 0xFFC0 2E88 CAN_MB21_DATA2 0xFFC0 2EA8 CAN_MB22_DATA2 0xFFC0 2EC8 CAN_MB23_DATA2 0xFFC0 2EE8 CAN_MB24_DATA2 0xFFC0 2F08 CAN_MB25_DATA2 0xFFC0 2F28 CAN_MB26_DATA2 0xFFC0 2F48 CAN_MB27_DATA2 0xFFC0 2F68...
Page 776 CAN Register Definitions Mailbox Word 1 Register (CAN_MBxx_DATA1) 15 14 13 12 11 10 Reset = 0xXXXX For memory- mapped addresses, see Table 17-18. Data Field Byte 4[7:0] Data Field Byte 5[7:0] Figure 17-28. Mailbox Word 1 Register Table 17-18. Mailbox Word 1 Register Memory-Mapped Addresses Register Name Memory-Mapped Address...
Page 777 CAN Module Table 17-18. Mailbox Word 1 Register Memory-Mapped Addresses (Cont’d) Register Name Memory-Mapped Address CAN_MB18_DATA1 0xFFC0 2E44 CAN_MB19_DATA1 0xFFC0 2E64 CAN_MB20_DATA1 0xFFC0 2E84 CAN_MB21_DATA1 0xFFC0 2EA4 CAN_MB22_DATA1 0xFFC0 2EC4 CAN_MB23_DATA1 0xFFC0 2EE4 CAN_MB24_DATA1 0xFFC0 2F04 CAN_MB25_DATA1 0xFFC0 2F24 CAN_MB26_DATA1 0xFFC0 2F44 CAN_MB27_DATA1 0xFFC0 2F64...
Page 778 CAN Register Definitions Mailbox Word 0 Register (CAN_MBxx_DATA0) 15 14 13 12 11 10 Reset = 0xXXXX For memory- mapped addresses, see Table 17-19. Data Field Byte 6[7:0] Data Field Byte 7[7:0] Figure 17-29. Mailbox Word 0 Register Table 17-19. Mailbox Word 0 Register Memory-Mapped Addresses Register Name Memory-Mapped Address...
Page 779 CAN Module Table 17-19. Mailbox Word 0 Register Memory-Mapped Addresses (Cont’d) Register Name Memory-Mapped Address CAN_MB18_DATA0 0xFFC0 2E40 CAN_MB19_DATA0 0xFFC0 2E60 CAN_MB20_DATA0 0xFFC0 2E80 CAN_MB21_DATA0 0xFFC0 2EA0 CAN_MB22_DATA0 0xFFC0 2EC0 CAN_MB23_DATA0 0xFFC0 2EE0 CAN_MB24_DATA0 0xFFC0 2F00 CAN_MB25_DATA0 0xFFC0 2F20 CAN_MB26_DATA0 0xFFC0 2F40 CAN_MB27_DATA0 0xFFC0 2F60...
Page 780: Mailbox Control Registers
CAN Register Definitions Mailbox Control Registers Figure 17-30 through Figure 17-56 show the mailbox control registers. CAN_MCx Registers Mailbox Configuration Register 1 (CAN_MC1) For all bits, 0 - Mailbox disabled, 1 - Mailbox enabled 15 14 13 12 11 10 Reset = 0x0000 0xFFC0 2A00 MC15...
Page 781: Can_Mdx Registers
CAN Module CAN_MDx Registers Mailbox Direction Register 1 (CAN_MD1) For all bits, 0 - Mailbox configured as transmit mode, 1 - Mailbox configured as receive mode 15 14 13 12 11 10 Reset = 0x00FF 0xFFC0 2A04 MD15 MD0 - RO MD14 MD1 - RO MD13...
Page 782: Can_Rmpx Register
CAN Register Definitions CAN_RMPx Register Receive Message Pending Register 1 (CAN_RMP1) All bits are W1C 15 14 13 12 11 10 Reset = 0x0000 0xFFC0 2A18 RMP15 RMP0 RMP14 RMP1 RMP13 RMP2 RMP12 RMP3 RMP11 RMP4 RMP10 RMP5 RMP9 RMP6 RMP8 RMP7 Figure 17-34.
Page 783: Can_Rmlx Register
CAN Module CAN_RMLx Register Receive Message Lost Register 1 (CAN_RML1) 15 14 13 12 11 10 Reset = 0x0000 0xFFC0 2A1C RML15 RML0 RML14 RML1 RML13 RML2 RML12 RML3 RML11 RML4 RML10 RML5 RML9 RML6 RML8 RML7 Figure 17-36. Receive Message Lost Register 1 Receive Message Lost Register 2 (CAN_RML2) 15 14 13 12 11 10 Reset = 0x0000...
Page 784: Can_Opssx Register
CAN Register Definitions CAN_OPSSx Register Overwrite Protection/Single Shot Transmission Register 1 (CAN_OPSS1) 15 14 13 12 11 10 Reset = 0x0000 0xFFC0 2A30 OPSS15 OPSS0 OPSS14 OPSS1 OPSS13 OPSS2 OPSS12 OPSS3 OPSS11 OPSS4 OPSS10 OPSS5 OPSS9 OPSS6 OPSS8 OPSS7 Figure 17-38. Overwrite Protection/Single Shot Transmission Register 1 Overwrite Protection/Single Shot Transmission Register 2 (CAN_OPSS2) 15 14 13 12 11 10 Reset = 0x0000...
Page 785: Can_Trsx Registers
CAN Module CAN_TRSx Registers Transmission Request Set Register 1 (CAN_TRS1) 15 14 13 12 11 10 Reset = 0x0000 0xFFC0 2A08 TRS15 TRS0 - RO TRS14 TRS1 - RO TRS13 TRS2 - RO TRS12 TRS3 - RO TRS11 TRS4 - RO TRS10 TRS5 - RO TRS9...
Page 786: Can_Trrx Registers
CAN Register Definitions CAN_TRRx Registers Transmission Request Reset Register 1 (CAN_TRR1) 15 14 13 12 11 10 Reset = 0x0000 0xFFC0 2A0C TRR15 TRR0 - RO TRR14 TRR1 - RO TRR13 TRR2 - RO TRR12 TRR3 - RO TRR11 TRR4 - RO TRR10 TRR5 - RO TRR9...
Page 787: Can_Aax Register
CAN Module CAN_AAx Register Abort Acknowledge Register 1 (CAN_AA1) All bits are W1C 15 14 13 12 11 10 Reset = 0x0000 0xFFC0 2A14 AA15 AA0 - RO AA14 AA1 - RO AA13 AA2 - RO AA12 AA3 - RO AA11 AA4 - RO AA10...
Page 788: Can_Tax Register
CAN Register Definitions CAN_TAx Register Transmission Acknowledge Register 1 (CAN_TA1) All bits are W1C 15 14 13 12 11 10 Reset = 0x0000 0xFFC0 2A10 TA15 TA0 - RO TA14 TA1 - RO TA13 TA2 - RO TA12 TA3 - RO TA11 TA4 - RO TA10...
Page 789: Can_Mbtd Register
CAN Module CAN_MBTD Register Temporary Mailbox Disable Feature Register (CAN_MBTD) 15 14 13 12 11 10 0xFFC0 2AAC Reset = 0x0000 TDPTR[4:0] (Temporary Disable Pointer) TDA (Temporary Disable Acknowledge) TDR (Temporary Disable Request) Figure 17-48. Temporary Mailbox Disable Register CAN_RFHx Registers Remote Frame Handling Register 1 (CAN_RFH1) 15 14 13 12 11 10 Reset = 0x0000...
Page 790: Can_Mbimx Registers
CAN Register Definitions Remote Frame Handling Register 2 (CAN_RFH2) 15 14 13 12 11 10 Reset = 0x0000 0xFFC0 2A6C RFH31 - RO RFH16 RFH30 - RO RFH17 RFH29 - RO RFH18 RFH28 - RO RFH19 RFH27 - RO RFH20 RFH26 - RO RFH21 RFH25 - RO...
Page 791: Can_Mbtifx Registers
CAN Module Mailbox Interrupt Mask Register 2 (CAN_MBIM2) 15 14 13 12 11 10 Reset = 0x0000 0xFFC0 2A68 MBIM31 MBIM16 MBIM30 MBIM17 MBIM29 MBIM18 MBIM28 MBIM19 MBIM27 MBIM20 MBIM26 MBIM21 MBIM25 MBIM22 MBIM24 MBIM23 Figure 17-52. Mailbox Interrupt Mask Register 2 CAN_MBTIFx Registers Mailbox Transmit Interrupt Flag Register 1 (CAN_MBTIF1) All bits are W1C...
Page 792: Can_Mbrifx Registers
CAN Register Definitions Mailbox Transmit Interrupt Flag Register 2 (CAN_MBTIF2) All bits are W1C 15 14 13 12 11 10 Reset = 0x0000 0xFFC0 2A60 MBTIF31 MBTIF16 MBTIF30 MBTIF17 MBTIF29 MBTIF18 MBTIF28 MBTIF19 MBTIF27 MBTIF20 MBTIF26 MBTIF21 MBTIF25 MBTIF22 MBTIF24 MBTIF23 Figure 17-54.
Page 793 CAN Module Mailbox Receive Interrupt Flag Register 2 (CAN_MBRIF2) All bits are W1C 15 14 13 12 11 10 Reset = 0x0000 0xFFC0 2A64 MBRIF31 - RO MBRIF16 MBRIF30 - RO MBRIF17 MBRIF29 - RO MBRIF18 MBRIF28 - RO MBRIF19 MBRIF27 - RO MBRIF20 MBRIF26 - RO...
Page 794: Universal Counter Registers
CAN Register Definitions Universal Counter Registers Figure 17-57 through Figure 17-59 show the universal counter registers. CAN_UCCNF Register Universal Counter Configuration Mode Register (CAN_UCCNF) 15 14 13 12 11 10 Reset = 0x0000 0xFFC0 2ACC UCCNF[3:0] (Universal Coun- UCE (Universal Counter ter Configuration) Enable) 0x0 - Reserved...
Page 795: Can_Uccnt Register
CAN Module CAN_UCCNT Register Universal Counter Register (CAN_UCCNT) 15 14 13 12 11 10 0xFFC0 2AC4 Reset = 0x0000 UCCNT[15:0] Figure 17-58. Universal Counter Register CAN_UCRC Register Universal Counter Reload/Capture Register (CAN_UCRC) 15 14 13 12 11 10 0xFFC0 2AC8 Reset = 0x0000 UCVAL[15:0] Figure 17-59.
Page 796: Error Registers
CAN Register Definitions Error Registers Figure 17-60 through Figure 17-62 show the CAN error registers. CAN_CEC Register CAN Error Counter Register (CAN_CEC) 15 14 13 12 11 10 0xFFC0 2A90 Reset = 0x0000 TXECNT[7:0] (Transmit Error RXECNT[7:0] (Receive Error Counter) Counter) Figure 17-60.
Page 797: Programming Examples
CAN Module Programming Examples The following CAN code examples (Listing 17-2 through Listing 17-4) show how to program the CAN hardware and timing, initialize mailboxes, perform transfers, and service interrupts. Each of these code examples assumes that the appropriate header file is included in the source code (that is, for ADSP-BF537 projects).
Page 798: Initializing And Enabling Can Mailboxes
Programming Examples R0 = 0x0334(Z); /* SJW = 3, TSEG2 = 3, TSEG1 = 4 */ W[P0] = R0; SSYNC; /* =================================================== ** CAN_CLOCK - Calculate Prescaler (BRP) ** Assume a 500kbps CAN rate is desired, which means ** the duration of the bit on the CAN bus (tBIT) is ** 2us.
Page 799 CAN Module Listing 17-3. Initializing and Enabling Mailboxes CAN_Initialize_Mailboxes: P0.H = HI(CAN_MD1); /* Configure Mailbox Direction */ P0.L = LO(CAN_MD1); R0 = W[P0](Z); BITCLR(R0, BITPOS(MD8)); /* Set MB08 for Transmit */ BITSET(R0, BITPOS(MD9)); /* Set MB09 for Receive */ W[P0] = R0; SSYNC;...
Page 800: Initiating Can Transfers And Processing Interrupts
Programming Examples R0 = 0xAABB(Z); P0.L = LO(CAN_MB_DATA3(8)); W[P0] = R0; /* Byte0 = 0xAA, Byte1 = 0xBB */ R0 = 1; P0.L = LO(CAN_MB_DATA2(8)); W[P0] = R0; /* Initialize Count to 1 */ /* Initialize Mailbox 9 For Receive */ R0 = 0x007 <<...
Page 801 CAN Module Listing 17-4. CAN Transfers and Interrupts CAN_SetupIRQs_and_Transfer: P0.H = HI(CAN_MBIM1); P0.L = LO(CAN_MBIM1); R0 = 0; BITSET(R0, BITPOS(MBIM8)); /* Enable Mailbox Interrupts */ BITSET(R0, BITPOS(MBIM9)); /* for Mailboxes 8 and 9 */ W[P0] = R0; SSYNC; /* Leave CAN Configuration Mode (Clear CCR) */ P0.L = LO(CAN_CONTROL);...
Page 802 Programming Examples ** =================================================== CAN_TX_HANDLER: [--SP] = (R7:6, P5:5); /* Save Clobbered Registers */ [--SP] = ASTAT; P5.H = HI(CAN_MBTIF1); P5.L = LO(CAN_MBTIF1); R7 = MBTIF8; W[P5] = R7; /* Clear Interrupt Request Bit for MB08 */ P5.L = LO(CAN_MB_DATA2(8)); R7 = W[P5](Z);...
Page 803 CAN Module /* =================================================== ** CAN_RX_HANDLER ** ISR clears the interrupt request from MB9, writes ** new data to be sent, and requests to send again ** =================================================== CAN_RX_HANDLER: [--SP] = (R7:7, P5:4); /* Save Clobbered Registers */ [--SP] = ASTAT; P4.H = CAN_RX_WORD;...
Page 804 Programming Examples 17-92 ADSP-BF50x Blackfin Processor Hardware Reference...
Page 805: Spi-Compatible Port Controller
Specific Information for the ADSP-BF50x For details regarding the number of SPIs for the ADSP-BF50x product, refer to ADSP-BF504, ADSP-BF504F, ADSP-BF506F Embedded Processor Data Sheet. For SPI DMA channel assignments, refer to Table 7-7 on page 7-105 Chapter 7, “Direct Memory...
Page 806: Overview
Overview Overview The SPI port provides an I/O interface to a wide variety of SPI-compati- ble peripheral devices. With a range of configurable options, the SPI port provides a glueless hardware interface with other SPI-compatible devices. SPI is a four-wire interface consisting of two data signals, a device select signal, and a clock signal.
Page 807: Interface Overview
SPI-Compatible Port Controller Typical SPI-compatible peripheral devices that can be used to interface to the SPI-compatible interface include: • Other CPUs or microcontrollers • Codecs • A/D converters • D/A converters • Sample rate converters • SP/DIF or AES/EBU digital audio transmitters and receivers •...
Page 808: External Interface
Interface Overview SPISS MOSI MISO INTERNAL CLOCK GENERATOR SPI INTERFACE LOGIC SPI_CTL SPI_STAT SPI_FLG SPI_BAUD SPI_SHADOW SHIFT REGISTER SPI_TDBR SPI_RDBR SPI IRQ TRANSMIT RECEIVE OR DMA REGISTER REGISTER REQUEST FOUR-DEEP FIFO Figure 18-1. SPI Block Diagram External Interface The following sections describe the components of the SPI external inter- face, which includes the following signals: •...
Page 809: Master-Out, Slave-In (Mosi) Signal
SPI-Compatible Port Controller SPI Clock Signal (SCK) signal is the serial clock signal. This control signal is driven by the master and controls the rate at which data is transferred. The master may transmit data at a variety of bit rates. The signal cycles once for each bit transmitted.
Page 810: Spi Slave Select Input Signal (Spiss)
Interface Overview The SPI configuration example in Figure 18-2 illustrates how the proces- sor can be used as the slave SPI device. The 8-bit host microcontroller is the SPI master.  The processor can be booted through its SPI interface to allow user application code and data to be downloaded before runtime.
Page 811: Spi Slave Select Enable Output Signals
SPI-Compatible Port Controller (CPOL = 1) SPISS (TO SLAVE) Figure 18-3. SPI Timing For a master device with = 0, the slave select output is inactive (high) CPHA for at least one-half the period. In this case, T1 and T2 will each always be equal to one-half the period.
Page 812: Slave Select Inputs
Interface Overview In slave mode, the bits have no effect, and each SPI uses the SPI_FLG input as a slave select. Just as in the master mode case, the port pin SPISS associated with must first be configured appropriately before use. SPISS Figure 18-14 on page 18-38 shows the...
Page 813 SPI-Compatible Port Controller In cases 1 and 2, the processor is the master and the seven microcon- trollers/peripherals with SPI interfaces are slaves. The processor can: 1. Transmit to all seven SPI devices at the same time in a broadcast mode.
Page 814 Interface Overview Figure 18-4 shows one processor as a master with three processors (or other SPI-compatible devices) as slaves. SLAVE DEVICE SLAVE DEVICE SLAVE DEVICE SPISS SPISS SPISS MISO MOSI MISO SCK MOSI MISO SCK MOSI SPISS MISO SCK MOSI PF/PG/PH PF/PG/PH MASTER...
Page 815: Internal Interfaces
SPI-Compatible Port Controller When using DMA for SPI transmit, the interrupt signi- DMA_DONE fies that the DMA FIFO is empty. However, at this point there may still be data in the SPI DMA FIFO waiting to be transmitted. Therefore, software needs to poll in the register until SPI_STAT...
Page 816: Description Of Operation
Description of Operation  When using DMA for SPI transmit, the interrupt signi- DMA_DONE fies that the DMA FIFO is empty. However, at this point there may still be data in the SPI DMA FIFO waiting to be transmitted. Therefore, software needs to poll in the register until SPI_STAT...
Page 817 SPI-Compatible Port Controller CLOCK PHASE (CPHA) CPHA = 0 CPHA = 1 MODE 0 MODE 1 SAMPLE DRIVE DRIVE SAMPLE EDGE EDGE EDGE EDGE MODE 2 MODE 3 SAMPLE DRIVE DRIVE SAMPLE EDGE EDGE EDGE EDGE Figure 18-5. SPI Modes of Operation The clock polarity and the clock phase should be identical for the master device and the slave device involved in the communication link.
Page 818 Description of Operation Figure 18-6 shows the SPI transfer protocol for = 0. Note starts CPHA toggling in the middle of the data transfer, = 0, and = 0. SIZE LSBF (CPOL = 0) (CPOL = 1) MOSI (FROM MASTER) MISO (FROM SLAVE) SPISS...
Page 819: Spi General Operation
SPI-Compatible Port Controller SPI General Operation The SPI can be used in single master as well as multimaster environments. , and the signals are all tied together in both configura- MOSI MISO tions. SPI transmission and reception are always enabled simultaneously, unless the broadcast mode has been selected.
Page 820: Clock Signals
Description of Operation the slave and accepts new data from the master into its shift register, while it transmits requested data out of the shift register through its SPI trans- mit data pin. Multiple processors can take turns being the master device, as can other microcontrollers or microprocessors.
Page 821: Interrupt Output
SPI-Compatible Port Controller clock phase relative to data are programmable in the register and SPI_CTL define the transfer format. See Figure 18-5 on page 18-13. Interrupt Output The SPI has two interrupt output signals: a data interrupt and an error interrupt.
Page 822: Master Mode Operation (Non-Dma)
Functional Description Master Mode Operation (Non-DMA) When the SPI is configured as a master (and DMA mode is not selected), the interface operates in the following manner. 1. The core writes to the appropriate port register(s) to properly con- figure the SPI interface for master mode operation. The required pins are configured for SPI use as slave-select outputs.
Page 823: Transfer Initiation From Master (Transfer Modes)
SPI-Compatible Port Controller If the transmit buffer remains empty or the receive buffer remains full, the device operates according to the states of the bits in SPI_CTL = 1 and the transmit buffer is empty, the device repeatedly transmits zeros on the pin.
Page 824: Slave Mode Operation (Non-Dma)
Functional Description Table 18-1. Transfer Initiation TIMOD Function Transfer Initiated Upon Action, Interrupt Transmit and Initiate new single word trans- Interrupt is active when the b#00 receive fer upon read of SPI_RDBR receive buffer is full. and previous transfer com- pleted.
Page 825 SPI-Compatible Port Controller These steps illustrate SPI operation in the slave mode: 1. The core writes to the appropriate port register(s) to properly con- figure the SPI for slave mode operation. 2. The core writes to to define the mode of the serial link to SPI_CTL be the same as the mode set up in the SPI master.
Page 826: Slave Ready For A Transfer
Programming Model Slave Ready for a Transfer When a device is enabled as a slave, the actions shown in Table 18-2 necessary to prepare the device for a new transfer. Table 18-2. Transfer Preparation TIMOD Function Action, Interrupt Transmit and Interrupt is active when the receive buffer is full.
Page 827 SPI-Compatible Port Controller finished after it sends the last data and simultaneously receives the last data bit. A transfer for a slave device ends after the last sampling edge of bit defines when the receive buffer can be read. The defines when the transmit buffer can be filled.
Page 828: Master Mode Dma Operation
Programming Model software performs a dummy read from the register to initiate the SPI_RDBR first transfer. If the first transfer is used for data transmission, software should write the value to be transmitted into the register before SPI_TDBR performing the dummy read. If the transmitted value is arbitrary, it is good practice to set the bit in the register to ensure zero data is...
Page 829 SPI-Compatible Port Controller 3. The processor core writes to the register, setting one or SPI_FLG more of the SPI flag select bits ( FLSx 4. The processor core writes to the registers, SPI_BAUD SPI_CTL enabling the device as a master and configuring the SPI system by specifying the appropriate word length, transfer format, baud rate, and so on.
Page 830 Programming Model In transmit mode, as long as there is room in the SPI DMA FIFO (the FIFO is not full), the SPI continues to request a DMA read from memory. The DMA engine continues to read a word from memory and write to the SPI DMA FIFO until the SPI DMA word count register transitions from “1”...
Page 831: Slave Mode Dma Operation
SPI-Compatible Port Controller to the register during an active SPI receive DMA operation are SPI_TDBR allowed. Reads from the register are allowed at any time. SPI_RDBR DMA requests are generated when the DMA FIFO is not empty (when ), or when the DMA FIFO is not full (when TIMOD b#10 TIMOD...
Page 832 Programming Model 4. If configured for receive, once the slave select input is active, the slave starts receiving and transmitting data on edges. The value in the shift register is loaded into the register at the end SPI_RDBR of the transfer. As the SPI reads data from the register SPI_RDBR and writes to the SPI DMA FIFO, it requests a DMA write to...
Page 833 SPI-Compatible Port Controller For receive DMA operations, if the DMA engine is unable to keep up with the receive datastream, the receive buffer operates according to the state of bit in the register. If = 1 and the DMA FIFO is full, the SPI_CTL device continues to receive new data from the pin, overwriting the...
Page 834 Programming Model WRITE TO PORT REGISTERS TO ENABLE SPI SIGNALS AND SELECT THE REQUIRED SIGNALS. WRITE TO PORT REGISTERS TO ENABLE MASTER MULTISLAVE AND SELECT THE APPROPRIATE SLAVE MASTER OR SLAVE? SUPPORT? SELECT SIGNALS. SLAVE, MSTR = 0 WRITE SPI_FLG TO SET APPROPRIATE FLSx BITS WRITE SPI_BAUD TO SET DESIRED SPI BIT RATE MSTR = 1 WRITE SPI_CTL TO CONFIGURE SPI HARDWARE AND ENABLE SPI PORT...
Page 835 SPI-Compatible Port Controller WRITE TO PORT REGISTERS TO ENABLE SPI SIGNALS AND SELECT THE REQUIRED SIGNALS. WRITE DESIRED DMA CHANNEL'S DMA_PERIPHERAL_MAP TO SET AS SPI. (REPLACE ALL MENTION OF DMA7 REGISTER NAMES IN THIS FLOW CHART WITH CHOSEN DMAx PREFIX.) WRITE DMA7_CONFIG TO CONFIGURE DMA ENGINE 0x4 ARRAY 0x6 SMALL LIST...
Page 836 Programming Model WRITE DMA REGISTERS: 2D DMA? DMA7_Y_COUNT DMA7_Y_MODIFY SLAVE, MSTR = 0 IS SPI MASTER OR SLAVE? MASTER WRITE TO PORT REGISTERS MULTI-SLAVE TO ENABLE SLAVES SUPPORT? WRITE SPI_FLG TO SET APPROPRIATE FLSx BITS WRITE SPI_BAUD TO SET DESIRED SPI BIT RATE MSTR = 1 WRITE SPI_CTL TO CONFIGURE SPI PORT WRITE SPI_FLG...
Page 837 SPI-Compatible Port Controller CLEAR INTERRUPT BY INTERRUPT WRITING THE DMA_DONE REQUESTED? BIT IN DMA7_IRQ_STATUS TERMINATE DMA? FLOW = STOP WRITE DMA7_CONFIG TO ENABLE DMA AGAIN TX OR RX DMA? WAIT FOR DMA_RUN = 0 IN DMA7_IRQ_STATUS WAIT FOR TWO STRAIGHT READS OF TXS = 0 IN SPI_STAT WAIT FOR SPIF = 1 IN SPI_STAT WRITE SPI_FLG TO...
Page 838: Spi Registers
SPI Registers SPI Registers The SPI peripheral includes a number of user-accessible registers. Some of these registers are also accessible through the DMA bus. Four registers contain control and status information: , and SPI_BAUD SPI_CTL SPI_FLG . Two registers are used for buffering receive and transmit data: SPI_STAT .
Page 839: Spi Baud Rate (Spi_Baud) Register
SPI-Compatible Port Controller SPI Baud Rate (SPI_BAUD) Register register is used to set the bit transfer rate for a master SPI_BAUD device. When configured as a slave, the value written to this register is ignored. The serial clock frequency is determined by this formula: frequency = (peripheral clock frequency )/(2 ×...
Page 840: Spi Control (Spi_Ctl) Register
SPI Registers SPI Control (SPI_CTL) Register register is used to configure and enable the SPI system. This SPI_CTL register is used to enable the SPI interface, select the device as a master or slave, and determine the data transfer format and word size. The term “word”...
Page 841 SPI-Compatible Port Controller Figure 18-13 provides the bit descriptions for SPI_CTL SPI Control Register (SPI_CTL) 15 14 13 12 11 10 Reset = 0x0400 SPE (SPI Enable) TIMOD[1:0] (Transfer Initiation 0 - Disabled Mode) 1 - Enabled 00 - Start transfer with read of SPI_RDBR, interrupt when WOM (Write Open Drain SPI_RDBR is full...
Page 842: Spi Flag (Spi_Flg) Register
SPI Registers SPI Flag (SPI_FLG) Register register consists of two sets of bits that function as follows. SPI_FLG SPI Flag Register (SPI_FLG) 15 14 13 12 11 10 Reset = 0xFF00 FLG7 (Slave FLS1 (Slave Select Enable 1) Select Value 7) 0 - SPISSEL1 disabled SPISSEL7 value 1 - SPISSEL1 enabled...
Page 843 SPI-Compatible Port Controller If the bit is not set, the general-purpose port registers configure and FLSx control the corresponding port pins. • Slave select value ( ) bits FLGx When a port pin is configured as a slave select output, the bits FLGx can determine the value driven onto the output.
Page 844: Spi Status (Spi_Stat) Register
SPI Registers SPI Status (SPI_STAT) Register The SPI_STAT register is used to detect when an SPI transfer is complete or if transmission/reception errors occur. The SPI_STAT register can be read at any time. SPI Status Register (SPI_STAT) 15 14 13 12 11 10 Reset = 0x0001 TXCOL (Transmit Collision Error) - W1C SPIF (SPI Finished) - RO...
Page 845: Mode Fault Error (Modf)
SPI-Compatible Port Controller Mode Fault Error (MODF) The MODF bit is set in SPI_STAT when the SPISS input pin of a device enabled as a master is driven low by some other device in the system. This occurs in multimaster systems when another device is also trying to be the master.
Page 846: Transmission Error (Txe)
SPI Registers configuring the direction of the port pins prior to configuring the SPI. This ensures that, once the error occurs and the slave selects are auto- MODF matically reconfigured as port pins, the slave select output drivers are disabled. Transmission Error (TXE) bit is set in when all the conditions of transmission are...
Page 847: Spi Receive Data Buffer (Spi_Rdbr) Register
SPI-Compatible Port Controller When the DMA is enabled for transmit operation, the DMA engine loads data into this register for transmission just prior to the beginning of a data transfer. A write to should not occur in this mode because this SPI_TDBR data will overwrite the DMA data to be transmitted.
Page 848: Spi Rdbr Shadow (Spi_Shadow) Register
SPI Registers register is cleared and an SPI transfer may be initiated (if SPI_STAT TIMOD b#00 SPI Receive Data Buffer Register (SPI_RDBR) Read Only 15 14 13 12 11 10 Reset = 0x0000 Receive Data Buffer[15:0] Figure 18-17. SPI Receive Data Buffer Register SPI RDBR Shadow (SPI_SHADOW) Register The SPI_SHADOW register is provided for use in debugging software.
Page 849: Programming Examples
SPI-Compatible Port Controller Programming Examples This section includes examples (Listing 18-1 through Listing 18-8) for both core-generated and DMA-based transfers. Each code example assumes that the appropriate processor header files are included. Core-Generated Transfer The following core-driven master-mode SPI example shows how to initial- ize the hardware, signal the start of a transfer, handle the interrupt and issue the next transfer, and generate a stop condition.
Page 850: Starting A Transfer
Programming Examples * TIMOD [1:0] = 00 : Transfer On RDBR Read. * SZ [2] = 0 : Send Last Word When TDBR Is Empty * GM [3] = 1 : Overwrite Previous Data If RDBR Is Full * PSSE [4] = 0 : Disables Slave-Select As Input (Master) * EMISO [5] = 0 : MISO Disabled For Output (Master)
Page 851: Post Transfer And Next Transfer
SPI-Compatible Port Controller Listing 18-2. Initiate Transfer Initiate_Transfer: P0.H = hi(SPI_FLG); P0.L = lo(SPI_FLG); R0 = W[P0] (Z); BITCLR (R0,0xF); /* FLG7 */ W[P0] = R0; /* Drive 0 on enabled slave-select pin */ P0.H = hi(SPI_TDBR); /* SPI Transmit Register */ P0.L = lo(SPI_TDBR);...
Page 852: Stopping
Programming Examples W[P0] = R0.l; /* Write that data to SPI_TDBR */ Kick_Off_Next: P0.H = hi(SPI_RDBR); /* SPI receive register */ P0.L = lo(SPI_RDBR); R0 = W[P0] (z); /* Read SPI receive register (also kicks off next transfer) */ W[P2++] = R0; /* Store received data to memory */ RTI;...
Page 853: Dma Initialization Sequence
SPI-Compatible Port Controller DMA Initialization Sequence The following code initializes the DMA to perform a 16-bit memory read DMA operation in autobuffer mode, and generates an interrupt request when the buffer has been sent. This code assumes that points to the start of the data buffer to be transmitted and that is a defined NUM_SAMPLES...
Page 854: Spi Initialization Sequence
Programming Examples SPI Initialization Sequence Before the SPI can transfer data, the registers must be configured as follows. Listing 18-6. SPI Initialization SPI_Register_Initialization: P0.H = hi(SPI_FLG); P0.L = lo(SPI_FLG); R0 = W[P0] (Z); BITSET (R0,0x7); /* FLS7 */ W[P0] = R0; /* Enable slave-select output pin */ P1.H = hi(SPI_BAUD);...
Page 855: Starting A Transfer
SPI-Compatible Port Controller * [15] 0 : RESERVED ***************************************************/ /* Configure SPI as MASTER */ R1 = 0x190B(z); /* Leave disabled until DMA is enabled */ P1.L = lo(SPI_CTL); W[P1] = R1; ssync; Starting a Transfer After the initialization procedure in the given master mode, a transfer begins following enabling of SPI.
Page 856 Programming Examples empty. If there is data in the SPI Transmit FIFO, it is loaded as soon as bit clears. A second consecutive read with the bit clear indi- cates the FIFO is empty and the last word is in the shift register. Finally, polling for the bit determines when the last bit of the last word has SPIF...
Page 857 SPI-Compatible Port Controller CC = R0 == 0; IF !CC JUMP Check_TXS; R2 = W[P0] (Z); /* Check if TXS stays clear for 2 reads */ R2 = R2 & R1; CC = R0 == 0; IF !CC JUMP Check_TXS; /* Wait for final word to transmit from SPI */ Final_Word: R0 = W[P0](Z);...
Page 858: Unique Information For The Adsp-Bf50X Processor
Unique Information for the ADSP-BF50x Processor Unique Information for the ADSP-BF50x Processor None. 18-54 ADSP-BF50x Blackfin Processor Hardware Reference...
Page 859: 19 Sport Controller
Specific Information for the ADSP-BF50x For details regarding the number of SPORTs for the ADSP-BF50x prod- uct, refer to ADSP-BF504, ADSP-BF504F, ADSP-BF506F Embedded Processor Data Sheet. For SPORT DMA channel assignments, refer to Table 7-7 on page 7-105 Chapter 7, “Direct Memory...
Page 860: Overview
Many processors provide compati- ble interfaces, including processors from Analog Devices and other manufacturers. Each SPORT has its own set of control registers and data buffers.
Page 861 SPORT Controller A SPORT offers these features and capabilities: • Provides independent transmit and receive functions. • Transfers serial data words from 3 to 32 bits in length, either MSB first or LSB first. • Provides alternate framing and control for interfacing to I S serial devices, as well as other audio formats (for example, left-justified stereo serial data).
Page 862: Interface Overview
Interface Overview • Provides direct memory access transfer to and from memory under DMA master control. DMA can be autobuffer-based (a repeated, identical range of transfers) or descriptor-based (individual or repeated ranges of transfers with differing DMA parameters). • Has a multichannel mode for TDM interfaces. A SPORT can receive and transmit data selectively from a time-division-multi- plexed serial bitstream on 128 contiguous channels from a stream of up to 1024 total channels.
Page 863 SPORT Controller is received, the data is optionally expanded, then automatically transferred to the register, and then into the RX FIFO where it is available SPORT_RX to the processor. Table 19-1 shows the signals for each SPORT. Table 19-1. SPORT Signals Description DTxPRI Transmit Data Primary...
Page 864 Interface Overview TX REGISTER RX REGISTER TX FIFO RX FIFO 4 x 32 OR 8 x 16 4 x 32 OR 8 x 16 SERIAL TX PRI TX SEC RX PRI RX SEC CONTROL HOLD REG HOLD REG HOLD REG HOLD REG COMPANDING COMPANDING...
Page 865 SPORT Controller The primary and secondary data pins, if enabled by a specific processor port configuration, provide a method to increase the data throughput of the serial port. They do not behave as totally separate SPORTs; rather, they operate in a synchronous manner (sharing clock and frame sync) but on separate data.
Page 866 Interface Overview BLACKFIN SPORT0 TSCLK0 TFS0 RSCLK0 RFS0 SERIAL DT0PRI DEVICE A DR0PRI (PRIMARY) SERIAL DT0SEC DEVICE B DR0SEC (SECONDARY) SPORT1 TSCLK1 RSCLK1 TFS1 (TDV1) RFS1 DT1PRI DR1PRI DT1SEC DR1SEC SERIAL SERIAL SERIAL DEVICE N DEVICE 2 DEVICE 1 Figure 19-2. Example SPORT Connections 1, 2 (SPORT0 is Standard Mode, SPORT1 is Multichannel Mode) 1 In multichannel mode, TFS functions as a transmit data valid (TDV) output.
Page 867: Sport Pin/Line Terminations
SPORT Controller Figure 19-3 shows an example of a stereo serial device with three transmit and two receive channels connected to a processor with two SPORTs. AD1836 STEREO SERIAL BLACKFIN DEVICE SPORT0 DLRCLK TSCLK0 DBCLK TFS0 RSCLK0 DSDATA1 DSDATA2 RFS0 DSDATA3 DT0PRI DR0PRI...
Page 868: Description Of Operation
Description of Operation Description of Operation This section describes general SPORT operation, illustrating the most common use of a SPORT. Since the SPORT functionality is configurable, this description represents just one of many possible configurations. Writing to a register readies the SPORT for transmission. The SPORT_TX signal initiates the transmission of serial data.
Page 869: Setting Sport Modes
SPORT Controller Clearing the enable bits disables the SPORTs and aborts TSPEN RSPEN any ongoing operations. Status bits are also cleared. Configuration bits remain unaffected and can be read by the software in order to be altered or overwritten. To disable the SPORT output clock, set the SPORT to be disabled.
Page 870 Description of Operation SPORT_TCR2 changes the operation of the frame sync pin to a left/right clock as required for I2S and left-justified stereo serial data. Setting this bit enables the SPORT to generate or accept the special LRCLK-style frame sync. All other SPORT control bits remain in effect and should be set appropriately.
Page 871 SPORT Controller Table 19-2. Stereo Serial Settings (Cont’d) Bit Field Stereo Audio Serial Scheme Left-Justified DSP Mode SLEN 2 – 31 2 – 31 2 – 31 RLSBIT RFSDIV 2 – Max 2 – Max 2 – Max (If internal FS is selected.) RXSE (Secondary Enable is available for RX and TX.) Note most bits shown as a 0 or 1 may be changed depending on the user’s...
Page 872 Description of Operation The secondary pins are useful extensions of the SPORT DRSEC DTSEC which pair well with stereo serial mode. Multiple I S streams of data can be transmitted or received using a single SPORT. Note the primary and secondary pins are synchronous, as they share clock and (frame LRCLK...
Page 873: Multichannel Operation
SPORT Controller RIGHT CHANNEL LEFT CHANNEL RSCLK DRPRI LEFT-JUSTIFIED MODE—3 TO 32 BITS PER CHANNEL LEFT CHANNEL RIGHT CHANNEL RSCLK DRPRI I 2 S MODE—3 TO 32 BITS PER CHANNEL RSCLK DRPRI DSP MODE—3 TO 32 BITS PER CHANNEL 1, 2, 3 Figure 19-5.
Page 874 Description of Operation total channels. RX and TX must use the same 128-channel region to selec- tively enable channels. The SPORT can do any of the following on each channel: • Transmit data • Receive data • Transmit and receive data •...
Page 875 SPORT Controller disable and then disable . Note both TSPEN RSPEN TSPEN RSPEN must be disabled before re-enabling. Disabling only TX or RX is not allowed. Figure 19-6 shows example timing for a multichannel transfer that has these characteristics: • Use TDM method where serial data is sent or received on different channels sharing the same serial bus •...
Page 876: Multichannel Enable
Description of Operation Multichannel Enable Setting the bit in the register enables multichannel MCMEN SPORT_MCM2 mode. When = 1, multichannel operation is enabled; when MCMEN = 0, all multichannel operations are disabled. MCMEN  Setting the bit enables multichannel operation for both the MCMEN receive and transmit sides of the SPORT.
Page 877: Frame Syncs In Multichannel Mode
SPORT Controller Table 19-3. Multichannel Mode Configuration (Cont’d) SPORT_RCR1 or SPORT_TCR1 or Notes SPORT_RCR2 SPORT_TCR2 SLEN SLEN Set or clear both to same value RXSE TXSE Independent RSFSE TSFSE Both must be 0 RRFST TRFST Ignored Frame Syncs in Multichannel Mode All receiving and transmitting devices in a multichannel system must have the same timing reference.
Page 878: The Multichannel Frame
Description of Operation output-enabled signal for the data transmit pin. The SPORT drives multichannel mode whether or not is cleared. The pin in multi- ITFS channel mode still obeys the bit. If is set, the transmit data valid LTFS LTFS signal will be active low—a low signal on the pin indicates an active channel.
Page 879: Multichannel Frame Delay
SPORT Controller RSCLK FRAME SYNC CHANNEL DATA DATA IGNORED DATA IGNORED DATA IGNORED MULTICHANNEL FRAME SPORT_MCMCn REG FIELDS WINDOW WINDOW OFFSET SIZE UNITS: BITS WORDS MULTIPLES OF 8 WORDS RANGE: 0–15 0–1015 8–128 NOTE: FRAME LENGTH IS SET BY FRAME SYNC DIVIDE OR EXTERNAL FRAME SYNC PERIOD. Figure 19-7.
Page 880: Window Offset
Description of Operation window size of 8 channels. To calculate the active window size from the register, use this equation: WSIZE Number of words in active window = 8 × (WSIZE + 1) Since the DMA buffer size is always fixed, it is possible to define a smaller window size (for example, 32 words), resulting in a smaller DMA buffer size (in this example, 32 words instead of 128 words) to save DMA band- width.
Page 881: Channel Selection Register
SPORT Controller When the frame sync/data relationship is used ( = 1), the frame sync FSDR is expected to change on the falling edge of the clock and is sampled on the rising edge of the clock. This is true even though data received is sam- pled on the negative edge of the receive clock.
Page 882: Multichannel Dma Data Packing
Description of Operation Setting a particular bit in the register causes the SPORT to SPORT_MTCSn transmit the word in that channel’s position of the datastream. Clearing the bit in the register causes the SPORT’s data transmit pin SPORT_MTCSn to three-state during the time slot of that channel. Setting a particular bit in the register causes the SPORT to SPORT_MRCSn...
Page 883: Support For H.100 Standard Protocol
SPORT Controller transmitted or received would be placed at addresses 1 and 10 of the buf- fer, and the rest of the words in the DMA buffer would be ignored. This mode allows changing the number of enabled channels while the SPORT is enabled, with some caution.
Page 884: Clock And Frame Sync Frequencies
Functional Description register) chooses the applicable clock mode, which includes a SPORT_MCMC2 non-divide or bypass mode for normal operation. A value of = 00 MCCRM chooses non-divide or bypass mode (H.100-compatible), = 10 MCCRM chooses MVIP-90 clock divide (extract 2 MHz from 4 MHz), and = 11 chooses HMVIP clock divide (extract 8 MHz from 16 MHz).
Page 885: Maximum Clock Rate Restrictions
Externally generated late transmit frame syncs also experience a delay from arrival to data output, and this can limit the maximum serial clock speed. See ADSP-BF504, ADSP-BF504F, ADSP-BF506F Embedded Processor Data Sheet for exact timing specifications. ADSP-BF50x Blackfin Processor Hardware Reference...
Page 886: Word Length
Functional Description Word Length Each SPORT channel (transmit and receive) independently handles word lengths of 3 to 32 bits. The data is right-justified in the SPORT data reg- isters if it is fewer than 32 bits long, residing in the LSB positions. The value of the serial word length (SLEN) field in the SPORT_TCR2 and SPORT_RCR2 registers of each SPORT determines the word length according to this formula:...
Page 887: Companding
SPORT Controller Table 19-4. TDTYPE, RDTYPE, and Data Formatting TDTYPE or SPORT_TCR1 Data Formatting SPORT_RCR1 Data Formatting RDTYPE Normal operation Zero fill Reserved Sign extend Compand using -law Compand using -law Compand using A-law Compand using A-law These formats are applied to serial data words loaded into the SPORT_RX buffers.
Page 888: Clock Signal Options
Failure to allow for these clocks may result in a SPORT malfunction. See ADSP-BF504, ADSP-BF504F, ADSP-BF506F Embedded Processor Data Sheet for details. The first internal frame sync will occur one frame sync delay after the SPORTs are ready. External frame syncs can occur as soon as the SPORT is ready.
Page 889: Frame Sync Options
SPORT Controller Frame Sync Options Framing signals indicate the beginning of each serial word transfer. The framing signals for each SPORT are TFS (transmit frame sync) and RFS (receive frame sync). A variety of framing options are available; these options are configured in the SPORT configuration registers (SPORT_TCR1, SPORT_TCR2, SPORT_RCR1 and SPORT_RCR2).
Page 890: Internal Versus External Frame Syncs
Functional Description Figure 19-9 illustrates framed serial transfers, which have these characteristics: • TFSR and RFSR bits in the SPORT_TCR1 and SPORT_RCR1 registers determine framed or unframed mode. • Framed mode requires a framing signal for every word. Unframed mode ignores a framing signal after the first word. •...
Page 891: Active Low Versus Active High Frame Syncs
SPORT Controller When = 1 or = 1, the corresponding frame sync signal is gener- ITFS IRFS ated internally by the SPORT, and the pin or pin is an output. The frequency of the frame sync signal is determined by the value of the frame sync divisor in the register.
Page 892 Functional Description generated frame syncs. Setting = 0 selects the rising edge of TCKFE TSCLK drive data and internally generated frame syncs and selects the falling edge to sample externally generated frame syncs. TSCLK For the SPORT receiver, setting = 1 in the register RCKFE SPORT_RCR1...
Page 893: Early Versus Late Frame Syncs (Normal Versus Alternate Timing)
SPORT Controller Figure 19-11, = 1 and transmit and receive are con- TCKFE RCKFE nected together to share the same clock and frame syncs. DRIVE SAMPLE EDGE EDGE TSCLK = RSCLK INTERNAL OR EXTERNAL TFS = RFS INTERNAL OR EXTERNAL Figure 19-11.
Page 894 Functional Description framing mode. Continuous operation is restricted to word sizes of 4 or  longer ( SLEN When = 1 or = 1, late frame syncs are configured; this is the LATFS LARFS alternate mode of operation. In this mode, the first bit of the transmit data word is available and the first bit of the receive data word is sampled in the same serial clock cycle that the frame sync is asserted.
Page 895: Data Independent Transmit Frame Sync
SPORT Controller RSCLK TSCLK LATE FRAME SYNC EARLY FRAME SYNC DATA Figure 19-12. Normal Versus Alternate Framing Data Independent Transmit Frame Sync Normally the internally generated transmit frame sync signal ( ) is out- put only when the buffer has data ready to transmit. The SPORT_TX data-independent transmit frame sync select bit ( allows the contin-...
Page 896: Moving Data Between Sports And Memory
Functional Description Moving Data Between SPORTs and Memory Transmit and receive data can be transferred between the SPORTs and on-chip memory in one of two ways: with single word transfers or with DMA block transfers. If no SPORT DMA channel is enabled, the SPORT generates an interrupt every time it has received a data word or needs a data word to transmit.
Page 897: Peripheral Bus Errors
These timing examples show the relationships between the signals but are not scaled to show the actual timing parameters of the processor. Consult the ADSP-BF504, ADSP-BF504F, ADSP-BF506F Embedded Processor Data Sheet for actual timing parameters and values. These examples assume a word length of four bits ( = 3).
Page 898 Functional Description Figure 19-13 Figure 19-14, the normal framing mode is shown for non-continuous data (any number of cycles between TSCLK RSCLK words) and continuous data (no cycles between words). TSCLK SCLK RSCLK RFS OUTPUT RFS INPUT SPORT CONTROL REGISTER: BOTH INTERNAL FRAMING OPTION AND EXTERNAL FRAMING OPTION SHOWN.
Page 899 SPORT Controller RSCLK RFS OUTPUT RFS INPUT SPORT CONTROL REGISTER: BOTH INTERNAL FRAMING OPTION AND EXTERNAL FRAMING OPTION SHOWN. DR REPRESENTS DRPRI AND/OR DRSEC, DEPENDING ON DESIRED CONFIGURATION. Figure 19-15. SPORT Receive, Alternate Framing RSCLK RFS OUTPUT RFS INPUT SPORT CONTROL REGISTER: BOTH INTERNAL FRAMING OPTION AND EXTERNAL FRAMING OPTION SHOWN DR REPRESENTS DRPRI AND/OR DRSEC, DEPENDING ON DESIRED CONFIGURATION.
Page 900 Functional Description RSCLK DR REPRESENTS DRPRI AND/OR DRSEC, DEPENDING ON DESIRED CONFIGURATION. Figure 19-17. SPORT Receive, Unframed Mode, Normal Framing RSCLK DR REPRESENTS DRPRI AND/OR DRSEC, DEPENDING ON DESIRED CONFIGURATION. Figure 19-18. SPORT Receive, Unframed Mode, Alternate Framing Figure 19-19 through Figure 19-24 show framing for transmitting data...
Page 901 SPORT Controller TSCLK TFS OUTPUT TFS INPUT SPORT CONTROL REGISTER: BOTH INTERNAL FRAMING OPTION AND EXTERNAL FRAMING OPTION SHOWN. DT REPRESENTS DTPRI AND/OR DTSEC, DEPENDING ON DESIRED CONFIGURATION. Figure 19-19. SPORT Transmit, Normal Framing TSCLK TFS OUTPUT TFS INPUT SPORT CONTROL REGISTER: BOTH INTERNAL FRAMING OPTION AND EXTERNAL FRAMING OPTION SHOWN DT REPRESENTS DTPRI AND/OR DTSEC, DEPENDING ON DESIRED CONFIGURATION.
Page 902 Functional Description TSCLK TFS OUTPUT TFS INPUT SPORT CONTROL REGISTER: BOTH INTERNAL FRAMING OPTION AND EXTERNAL FRAMING OPTION SHOWN DT REPRESENTS DTPRI AND/OR DTSEC, DEPENDING ON DESIRED CONFIGURATION. Figure 19-22. SPORT Continuous Transmit, Alternate Framing Figure 19-23 Figure 19-24 show the transmit operation with normal framing and alternate framing, respectively, in the unframed mode.
Page 903: Sport Registers
SPORT Controller SPORT Registers The following sections describe the SPORT registers. Table 19-5 provides an overview of the available control registers. Table 19-5. SPORT Register Mapping Register Name Function Notes SPORT_TCR1 Primary transmit Bits [15:1] can only be written if configuration register bit 0 = 0 SPORT_TCR2...
Page 904: Register Writes And Effective Latency
SPORT Registers Table 19-5. SPORT Register Mapping (Cont’d) Register Name Function Notes SPORT_MCM2 Secondary multichannel Configure this register before mode configuration register enabling the SPORT SPORT_MRCSn Receive channel selection registers Select or deselect channels in a mul- tichannel frame SPORT_MTCSn Transmit channel selection registers Select or deselect channels in a mul- tichannel frame SPORT_CHNL...
Page 905: Sport Transmit Configuration (Sport_Tcr1 And Sport_Tcr2) Registers
SPORT Controller SPORT Transmit Configuration (SPORT_TCR1 and SPORT_TCR2) Registers The main control registers for the transmit portion of each SPORT are the transmit configuration registers, SPORT_TCR1 and SPORT_TCR2, shown in Figure 19-25 Figure 19-26. A SPORT is enabled for transmit if bit 0 ( ) of the transmit configu- TSPEN ration 1 register is set to 1.
Page 906 SPORT Registers SPORT Transmit Configuration 1 Register (SPORT_TCR1) 15 14 13 12 11 10 Reset = 0x0000 TCKFE (Clock Falling TSPEN (Transmit Enable) Edge Select) 0 - Transmit disabled 0 - Drive data and internal 1 - Transmit enabled frame syncs with rising ITCLK (Internal Transmit edge of TSCLK.
Page 907 SPORT Controller SPORT Transmit Configuration 2 Register (SPORT_TCR2) 15 14 13 12 11 10 Reset = 0x0000 SLEN[4:0] (SPORT Word Length) TRFST (Left/Right Order) 0 - Left stereo channel first 00000 - Illegal value 1 - Right stereo channel first 00001 - Illegal value Serial word length is value in TSFSE (Transmit Stereo...
Page 908 SPORT Registers  All SPORT control registers should be programmed before TSPEN set. Typical SPORT initialization code first writes all control regis- ters, including DMA control if applicable. The last step in the code is to write with all of the necessary bits, including SPORT_TCR1 TSPEN •...
Page 909 SPORT Controller must be programmed into the frame sync divider register; setting to 7 does not produce a frame sync pulse on each byte SLEN transmitted. • Internal transmit frame sync select. ( ). This bit selects ITFS whether the SPORT uses an internal (if set) or an external (if cleared).
Page 910: Sport Receive Configuration (Sport_Rcr1 And Sport_Rcr2) Registers
SPORT Registers • Late transmit frame sync. ( ). This bit configures late frame LATFS syncs (if set) or early frame syncs (if cleared). • Clock drive/sample edge select. ( ). This bit selects which TCKFE edge of the signal the SPORT uses for driving data, for driv- TCLKx ing internally generated frame syncs, and for sampling externally generated frame syncs.
Page 911 SPORT Controller SPORT Receive Configuration 1 Register (SPORT_RCR1) 15 14 13 12 11 10 Reset = 0x0000 RCKFE (Clock Falling RSPEN (Receive Enable) Edge Select) 0 - Receive disabled 0 - Drive internal frame sync 1 - Receive enabled on rising edge of RSCLK. IRCLK (Internal Receive Sample data and external Clock Select)
Page 912 SPORT Registers SPORT Receive Configuration 2 Register (SPORT_RCR2) 15 14 13 12 11 10 Reset = 0x0000 SLEN[4:0] (SPORT Word Length) RRFST (Left/Right Order) 0 - Left stereo channel first 00000 - Illegal value 1 - Right stereo channel first 00001 - Illegal value Serial word length is value in RSFSE (Receive Stereo...
Page 913 SPORT Controller  All SPORT control registers should be programmed before RSPEN set. Typical SPORT initialization code first writes all control regis- ters, including DMA control if applicable. The last step in the code is to write with all of the necessary bits, including SPORT_RCR1 RSPEN •...
Page 914: Data Word Formats
SPORT Registers • Low receive frame sync select. ( ). This bit selects an active low LRFS (if set) or active high (if cleared). • Late receive frame sync. ( ). This bit configures late frame LARFS syncs (if set) or early frame syncs (if cleared). •...
Page 915: Sport Transmit Data (Sport_Tx) Register
SPORT Controller SPORT Transmit Data (SPORT_TX) Register register is a write-only register. Reads produce a peripheral SPORT_TX bus error. Writes to this register cause writes into the transmitter FIFO.  The 16-bit wide FIFO is 8 deep for word length 16 and 4 deep for word length >...
Page 916 SPORT Registers The SPORT TX interrupt is asserted when = 1 and the TX FIFO TSPEN has room for additional words. This interrupt does not occur if SPORT DMA is enabled. The transmit underflow status bit ( ) is set in the register TUVF SPORT_STAT...
Page 917: Sport Receive Data (Sport_Rx) Register
SPORT Controller SPORT Transmit Data Register (SPORT_TX) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reset = 0x0000 0000 Transmit Data[31:16] 15 14 13 12 11 10 Transmit Data[15:0] Figure 19-30. SPORT Transmit Data Register SPORT Receive Data (SPORT_RX) Register register is a read-only register.
Page 918 SPORT Registers FROM Rx HOLD REGISTER FROM Rx HOLD REGISTER ONLY PRIMARY ENABLED PRIMARY AND PRIMARY SECONDARY DATA LENGTH <= 16 BITS SECONDARY ENABLED PRIMARY PRIMARY DATA LENGTH <= 16 BITS 8 WORDS OF PRIMARY SECONDARY PRIMARY DATA 4 WORDS OF PRIMARY PRIMARY IN FIFO...
Page 919 SPORT Controller The SPORT RX interrupt is generated when = 1 and the RX FIFO RSPEN has received words in it. When the core processor has read all the words in the FIFO, the RX interrupt is cleared. The SPORT RX interrupt is set only if SPORT RX DMA is disabled;...
Page 920: Sport Status (Sport_Stat) Register
SPORT Registers SPORT Status (SPORT_STAT) Register register is used to determine if the access to a SPORT RX SPORT_STAT or TX FIFO can be made by determining their full or empty status. This register is shown in Figure 19-33. bit in the register indicates whether there is room in SPORT_STAT the TX FIFO.
Page 921: Sport Transmit And Receive Serial Clock Divider (Sport_Tclkdiv And Sport_Rclkdiv) Registers
SPORT Controller SPORT Status Register (SPORT_STAT) 15 14 13 12 11 10 Reset = 0x0040 TXHRE (Transmit Hold Register Empty) RXNE (Receive FIFO Not Empty Status) 0 - Not empty 0 - Empty 1 - Empty 1 - Data present in FIFO TOVF (Sticky Transmit Overflow Status) - W1C RUVF (Sticky Receive Under- 0 - Disabled...
Page 922: Sport Transmit And Receive Frame Sync Divider (Sport_Tfsdiv And Sport_Rfsdiv) Registers
SPORT Registers SPORT Receive Serial Clock Divider Register (SPORT_RCLKDIV) 15 14 13 12 11 10 Reset = 0x0000 Serial Clock Divide Modulus[15:0] Figure 19-35. SPORT Receive Serial Clock Divider Register SPORT Transmit and Receive Frame Sync Divider (SPORT_TFSDIV and SPORT_RFSDIV) Registers The 16-bit SPORT_TFSDIV and SPORT_RFSDIV registers specify how many transmit or receive clock cycles are counted before generating a TFS or RFS pulse when the frame sync is internally generated.
Page 923: Sport Multichannel Configuration (Sport_Mcmc1 And Sport_Mcmc2) Registers
SPORT Controller SPORT Receive Frame Sync Divider Register (SPORT_RFSDIV) 15 14 13 12 11 10 Reset = 0x0000 Frame Sync Divider[15:0] Number of receive clock cycles counted before generating RFS pulse Figure 19-37. SPORT Receive Frame Sync Divider Register SPORT Multichannel Configuration (SPORT_MCMC1 and SPORT_MCMC2) Registers There are two multichannel configuration registers for each SPORT, shown in...
Page 924: Sport Current Channel (Sport_Chnl) Register
SPORT Registers SPORT Multichannel Configuration Register 2 (SPORT_MCMC2) 15 14 13 12 11 10 Reset = 0x0000 MFD[3:0] (Multichannel MCCRM[1:0] (2X Clock Frame Delay) Recovery Mode) 0x - Bypass mode Delay between frame sync pulse and the 10 - Recover 2 MHz clock first data bit in Multichannel mode from 4 MHz FSDR (Frame Sync to Data Relationship)
Page 925: Sport Multichannel Receive Selection (Sport_Mrcsn) Registers
SPORT Controller SPORT Current Channel Register (SPORT_CHNL) 15 14 13 12 11 10 Reset = 0x0000 CHNL[9:0] (Current Channel Indicator) Figure 19-40. SPORT Current Channel Register SPORT Multichannel Receive Selection (SPORT_MRCSn) Registers registers (shown in Figure 19-41) are used to enable and SPORT_MRCSn disable individual channels.
Page 926: Sport Multichannel Transmit Selection (Sport_Mtcsn) Registers
SPORT Registers SPORT Multichannel Receive Select Registers (SPORT_MRCSn) For all bits, 0 - Channel disabled, 1 - Channel enabled, so SPORT selects that word from multi- ple word block of data. Channel number Bit number in register MRCS0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...
Page 927: Programming Examples
SPORT Controller causes a SPORT controllers’ data transmit pins to three-state during the time slot of that channel. SPORT Multichannel Transmit Select Registers (SPORT_MTCSn) For all bits, 0 - Channel disabled, 1 - Channel enabled, so SPORT selects that word from multiple word block of data. Channel number Bit number in register MTCS0...
Page 928: Sport Initialization Sequence
Programming Examples ) and the DMA configuration. An example value is given SPORT_TCRn in the comments, but for the meaning of the individual bits the user is referred to the detailed explanation in this chapter. The example configures both the receive and the transmit section. Since they are completely independent, the code uses separate labels.
Page 929 SPORT Controller W[P0 + (SPORT0_TCR2 - SPORT0_TCR1)] = R1; /* Configuration register 1 (for instance 0x4E12 for inter- nally generated clk and framesync) */ R1 = SPORT_TRANSMIT_CONF_1; W[P0] = R1; ssync; /* NOTE: SPORT0 TX NOT enabled yet (bit 0 of TCR1 must be zero) */ Program_SPORT_RECEIVER_Registers: /* Set P0 to SPORT0 Base Address */ P0.h = hi(SPORT0_RCR1);...
Page 930: Dma Initialization Sequence
Programming Examples W[P0] = R1; ssync; /* NOTE: SPORT0 RX NOT enabled yet (bit 0 of RCR1 must be zero) */ DMA Initialization Sequence Next the DMA channels for receive (channel3 in this example) and for transmit (channel4 in this example) are set up for auto-buffered, one-dimensional, 32-bit transfers.
Page 931 SPORT Controller R1 = (length(rx_buf)/4)(z); W[P0 + (DMA3_X_COUNT - DMA3_CONFIG)] = R1; /* X_count register */ R1 = 4(z); /* 4 bytes in a 32-bit transfer */ W[P0 + (DMA3_X_MODIFY - DMA3_CONFIG)] = R1; /* X_modify register */ /* start_address register points to memory buffer to be filled */ R1.l = rx_buf;...
Page 932: Interrupt Servicing
Programming Examples W[P0 + (DMA4_X_MODIFY - DMA4_CONFIG)] = R1; /* X_modify register */ /* start_address register points to memory buffer to be transmitted from */ R1.l = tx_buf; R1.h = tx_buf; [P0 + (DMA4_START_ADDR - DMA4_CONFIG)] = R1; BITSET(R0,0); /* R0 still contains value of CONFIG register - set bit 0 */ W[P0] = R0;...
Page 933: Starting A Transfer
SPORT Controller TRANSMIT_ISR: [--SP] = RETI; /* nesting of interrupts */ /* clear DMA interrupt request */ P0.h = hi(DMA4_IRQ_STATUS); P0.l = lo(DMA4_IRQ_STATUS); = 1; W[P0] = R1.l; /* write one to clear */ RETI = [SP++]; rti; Starting a Transfer After the initialization procedure outlined in the previous sections, the receiver and transmitter are enabled.
Page 934: Unique Information For The Adsp-Bf50X Processor
Unique Information for the ADSP-BF50x Processor /* dummy wait loop (do nothing but waiting for interrupts) */ wait_forever: jump wait_forever: Unique Information for the ADSP-BF50x Processor None. 19-76 ADSP-BF50x Blackfin Processor Hardware Reference...
Page 935: Parallel Peripheral Interface
Specific Information for the ADSP-BF50x For details regarding the number of PPIs for the ADSP-BF50x product, refer to ADSP-BF504, ADSP-BF504F, ADSP-BF506F Embedded Processor Data Sheet. For PPI DMA channel assignments, refer to Table 7-7 on page 7-105 Chapter 7, “Direct Memory...
Page 936: Overview
Overview Overview The PPI is a half-duplex, bidirectional port accommodating up to 16 bits of data. It has a dedicated clock pin and three multiplexed frame sync pins. The highest system throughput is achieved with 8-bit data, since two 8-bit data samples can be packed as a single 16-bit word. In such a case, the earlier sample is placed in the 8 least significant bits (LSBs).
Page 937: Interface Overview
Parallel Peripheral Interface Interface Overview Figure 20-1 shows a block diagram of the PPI. PPI_CONTROL PPI_CLK PPI_COUNT PPI_STATUS DATA BUS PPI_DELAY CONTROLLER PPI_FRAME 16 BITS PACK/ SYNC GATE 16-DEEP UNPACK FIFO Figure 20-1. PPI Block Diagram pin accepts an external clock input. It cannot source a clock PPI_CLK internally.
Page 938: Description Of Operation
Description of Operation Description of Operation Table 20-1 shows all the possible modes of operation for the PPI. Table 20-1. PPI Possible Operating Modes PPI Mode # of Syncs PORT_DIR PORT_CFG XFR_TYPE POLC POLS FLD_ SEL RX mode, 0 frame 0 or 1 0 or syncs, external trig- RX mode, 0 frame...
Page 939: Itu-R 656 Modes
Parallel Peripheral Interface Table 20-1. PPI Possible Operating Modes (Cont’d) PPI Mode # of Syncs PORT_DIR PORT_CFG XFR_TYPE POLC POLS FLD_ SEL TX mode, 2 or 3 0 or 1 0 or internal frame syncs, FS3 sync’ed to FS1 assertion TX mode, 2 or 3 0 or 1 0 or internal frame...
Page 940 Functional Description 0-to-1 transition of . An entire field of video is comprised of active video + horizontal blanking (the space between an EAV and SAV code) and ver- tical blanking (the space where = 1). A field of video commences on a transition of the bit.
Page 941 Parallel Peripheral Interface LINE # LINE 4 VERTICAL BLANKING LINE FI ELD 1 (EAV) (SAV) NUMBER FIELD 1 1-3, ACTIVE VIDEO 266-282 LINE 266 4-19, VERTICAL 264-265 BLANKING FI ELD 2 20-263 FIELD 2 283-525 ACTIVE VIDEO LINE 3 LINE 1 VERTICAL BLANKING FI ELD 1...
Page 942 Functional Description • = 1 during vertical blanking • = 0 when not in vertical blanking • = 0 at SAV • = 1 at EAV • • • • In many applications, video streams other than the standard NTSC/PAL formats (for example, CIF, QCIF) can be employed.
Page 943: Itu-R 656 Input Modes
Parallel Peripheral Interface ITU-R 656 Input Modes Figure 20-4 shows a general illustration of data movement in the ITU-R 656 input modes. In the figure, the clock is either provided by the video source or supplied externally by the system. ITU-R 656 INPUT MODE '656 8- OR 10-BIT DATA WITH...
Page 944: Active Video Only
Functional Description but does not include the first EAV code that contains the assignment.  Note the first line transferred in after enabling the PPI will be miss- ing its first 4-byte preamble. However, subsequent lines and frames should have all control codes intact. One side benefit of this mode is that it enables a “loopback”...
Page 945: Itu-R 656 Output Mode
Parallel Peripheral Interface Note the VBI is split into two regions within each field. From the PPI’s standpoint, it considers these two separate regions as one contiguous space. However, keep in mind that frame synchronization begins at the start of field 1, which doesn’t necessarily correspond to the start of vertical blanking.
Page 946: General-Purpose Ppi Modes
Functional Description occur from the start of a frame until it decodes the end-of-frame condition (transition from = 1 to = 0). At this time, the actual number of lines processed is compared against the value in . If there is a mis- PPI_FRAME match, the bit in the...
Page 947 Parallel Peripheral Interface Table 20-3. General-Purpose PPI Modes (Cont’d) GP PPI Mode PPI_FS1 PPI_FS2 PPI_FS3 Data Direction Direction Direction Direction TX mode, 2 external frame syncs Input Input Not used Output TX mode, 1 internal frame sync Output Not used Not used Output TX mode, 2 or 3 internal frame syncs Output...
Page 948: Data Input (Rx) Modes
Functional Description  If the next frame sync arrives before the specified PPI_FS1 samples have been transferred out, the sync has priority PPI_COUNT and starts a new line transfer sequence. This situation can cause the DMA channel configuration to lose synchronization with the PPI transfer process.
Page 949: No Frame Syncs
Parallel Peripheral Interface No Frame Syncs These modes cover the set of applications where periodic frame syncs are not generated to frame the incoming data. There are two options for start- ing the data transfer, both configured by the register. PPI_CONTROL •...
Page 950: Or 3 Internal Frame Syncs
Functional Description Figure 20-7 shows a typical illustration of the system setup for this mode. CONVERTER PPI_FS1 FRAMESYNC 8–16 BITS DATA PPIx DATA PPI_CLK VIDEO SOURCE PPI_FS1 HSYNC PPI_FS2 VSYNC PPI_FS3 FIELD DATA 8–16 BITS DATA PPIx PPI_CLK Figure 20-7. RX Mode, External Frame Syncs The 3-sync mode shown at the bottom of Figure 20-7 supports video...
Page 951: Data Output (Tx) Modes
Parallel Peripheral Interface simply be left floating if not used. Figure 20-8 shows a sample application for this mode. IMAGE SOURCE PPI_FS1 HSYNC PPI_FS2 VSYNC PPIx DATA 8–16 BITS DATA PPI_CLK Figure 20-8. RX Mode, Internal Frame Syncs Data Output (TX) Modes The PPI supports several modes for data output.
Page 952: Or 2 External Frame Syncs
Functional Description PPIx RECEIVER 8- TO 16-BIT DATA PPI_CLK Figure 20-9. TX Mode, 0 Frame Syncs 1 or 2 External Frame Syncs In these modes, an external receiver can frame data sent from the PPI. Both 1-sync and 2-sync modes are supported. The top diagram in Figure 20-10 shows the 1-sync case, while the bottom diagram illustrates the 2-sync mode.
Page 953: 1, 2, Or 3 Internal Frame Syncs
Parallel Peripheral Interface 1, 2, or 3 Internal Frame Syncs The 1-sync mode is intended for interfacing to digital-to-analog convert- ers (DACs) with a single frame sync. The top part of Figure 20-11 shows an example of this type of connection. The 3-sync mode is useful for connecting to video and graphics displays, as shown in the bottom part of Figure...
Page 954 Functional Description the General-Purpose Timers chapter for information on how this is achieved on this processor. This allows for arbitrary pulse widths and peri- ods to be programmed for these signals using the existing registers. TIMERx This capability accommodates a wide range of timing needs. Note these PWM circuits are clocked by , not by (as during conven-...
Page 955: Modes With External Frame Syncs
Parallel Peripheral Interface To switch to another PPI mode not involving internal frame syncs: 1. Disable the PPI (using PPI_CONTROL 2. Disable the appropriate timer(s) (using TIMER_DISABLE Modes With External Frame Syncs In RX modes with external frame syncs, the pins PPI_FS1 PPI_FS2...
Page 956: Programming Model
Programming Model the timer itself can be configured and enabled for non-PPI use without affecting PPI operation in this mode. For more information, see the General-Purpose Timers chapter. Programming Model The following sections describe the PPI programming model. DMA Operation The PPI must be used with the processor’s DMA engine.
Page 957 Parallel Peripheral Interface contains 320 x 240 bytes (240 rows of 320 bytes each), these conditions hold: • Setting = 320, = 240, and = 1 (the XCOUNT YCOUNT DI_SEL DI_SEL bit is located in ) interrupts on every row transferred, DMA_CONFIG for the entire frame.
Page 958 Programming Model START PROGRAM 2D DMA? Y_COUNT AND Y_MODIFY Enable necessary PPI pins through PORT_MUX and PORT_FER registers PROGRAM PPI_DELAY PROGRAM TIMER(S) EXTERNAL INTERNAL FS? LINKED WITH FS TRIGGER? PROGRAM PPI_FRAME PROGRAM PPI_COUNT WRITE DMA_CONFIG TO ENABLE DMA WRITE PPI_CONTROL TO ENABLE PPI WRITE TIMER_ENABLE TO ENABLE TIMERS INTERNAL FS? Figure 20-12.
Page 959: Ppi Registers
Parallel Peripheral Interface PPI Registers The PPI has five memory-mapped registers (MMRs) that regulate its oper- ation. These registers are the PPI control register ( ), the PPI PPI_CONTROL status register ( ), the delay count register ( ), the PPI_STATUS PPI_DELAY transfer count register (...
Page 960 PPI Registers PPI Control Register (PPI_CONTROL) 15 14 13 12 11 10 Reset = 0x0000 PORT_EN (Enable) POLS 0 - PPI_FS1 and 0 - PPI disabled PPI_FS2 are treated 1 - PPI enabled as rising edge PORT_DIR (Direction) asserted 0 - PPI in Receive mode (input) 1 - PPI_FS1 and 1 - PPI in Transmit mode PPI_FS2 are treated...
Page 961 Parallel Peripheral Interface When the bit is set, the bit allows the PPI to ignore SKIP_EN SKIP_EO either the odd or the even elements in an input datastream. This is useful, for instance, when reading in a color video signal in YCbCr format (Cb, Y, Cr, Y, Cb, Y, Cr, Y...).
Page 962 PPI Registers • This is transferred onto the DMA bus: 0x00CE, 0x00FA, 0x00FE, 0x00CA,... For TX modes, setting enables unpacking of bytes. Consider this PACK_EN data in memory, to be transported out through the PPI via DMA: 0xFACE CAFE..(0xFA and 0xCA are the two most significant bits (MSBs) of their respec- tive 16-bit words) •...
Page 963: Ppi Status Register (Ppi_Status)
Parallel Peripheral Interface field configures the PPI for various modes of opera- XFR_TYPE[1:0] tion. Refer to Table 20-1 on page 20-4 to see how XFR_TYPE[1:0] interacts with other bits in to determine the PPI operating PPI_CONTROL mode. bit, when set, enables the PPI for operation. PORT_EN ...
Page 964 PPI Registers PPI Status Register (PPI_STATUS) 15 14 13 12 11 10 Reset = 0x0000 ERR_NCOR (Error LT_ERR_OVR (Horizontal Tracking Overflow Error) - W1C Not Corrected) - W1C Used only in ITU-R 656 Used only in ITU-R 656 modes modes 0 - No uncorrected 0 - No horizontal tracking preamble error...
Page 965 Parallel Peripheral Interface signals. In other words, the bit always reflects the current video field being processed by the PPI. bit is sticky and indicates, when set, that the PPI FIFO has over- flowed and can accept no more data. A FIFO overflow error generates a PPI error interrupt, unless this condition is masked off in the SIC_IMASK register.
Page 966: Ppi Delay Count Register (Ppi_Delay)
PPI Registers PPI Delay Count Register (PPI_DELAY) register, shown in Figure 20-15, can be used in all config- PPI_DELAY urations except ITU-R 656 modes and GP modes with 0 frame syncs. It contains a count of how many cycles to delay after assertion of PPI_CLK before starting to read in or write out data.
Page 967: Ppi Lines Per Frame Register (Ppi_Frame)
Parallel Peripheral Interface  Take care to ensure that the number of samples programmed into is in keeping with the number of samples expected dur- PPI_COUNT ing the “horizontal” interval specified by PPI_FS1 PPI Transfer Count Register (PPI_COUNT) 15 14 13 12 11 10 Reset = 0x0000 PPI_COUNT[15:0] In RX modes, holds one less...
Page 968: Programming Examples
Programming Examples However, the PPI still automatically reinitializes to count to the value pro- grammed in , and data transfer continues. PPI_FRAME  In ITU-R 656 modes, a frame start detect happens on the falling edge of , the field indicator. This occurs at the start of field 1. In RX mode with three external frame syncs, a frame start detect refers to a condition where a assertion is followed by an...
Page 969 Parallel Peripheral Interface Listing 20-1. Configure DMA Registers config_dma: /*Assumes PPI is mapped to DMA channel 0.*/ /* DMA0_START_ADDR */ R0.L = rx_buffer; R0.H = rx_buffer; P0.L = lo(DMA0_START_ADDR); P0.H = hi(DMA0_START_ADDR); [P0] = R0; /* DMA0_CONFIG */ R0.L = DI_EN | WNR; P0.L = lo(DMA0_CONFIG);...
Page 970 Programming Examples Listing 20-2. Configure PPI Registers config_ppi: /* PPI_CONTROL */ P0.L = lo(PPI_CONTROL); P0.H = hi(PPI_CONTROL); R0.L = 0x0004; W[P0] = R0.L; ssync; config_ppi.END: RTS; Listing 20-3. Enable DMA /* DMA0_CONFIG */ P0.L = lo(DMA0_CONFIG); P0.H = hi(DMA0_CONFIG); R0.L = W[P0]; bitset(R0,0);...
Page 971: Unique Information For The Adsp-Bf50X Processor
Parallel Peripheral Interface Listing 20-5. Clear DMA Completion Interrupt /* DMA0_IRQ_STATUS */ P2.L = lo(DMA0_IRQ_STATUS); P2.H = hi(DMA0_IRQ_STATUS); R2.L = W[P2]; BITSET(R2,0); W[P2] = R2.L; ssync; Unique Information for the ADSP-BF50x Processor None. ADSP-BF50x Blackfin Processor Hardware Reference 20-37...
Page 972 Unique Information for the ADSP-BF50x Processor 20-38 ADSP-BF50x Blackfin Processor Hardware Reference...
Page 973: Removable Storage Interface
21 REMOVABLE STORAGE INTERFACE This chapter describes the ADSP-BF50x Blackfin processor Removable Storage Interface (RSI) and includes the following sections: • “Overview” • “Interface Overview” on page 21-2 • “Description of Operation” on page 21-6 • “Functional Description” on page 21-9 •...
Page 974: Interface Overview
Interface Overview Features of the RSI interface include: • Support for a single SD or SDIO card • Support for one or more MMC cards (sharing the same interface) • Support for 1- and 4-bit SD modes (SPI mode is not supported) •...
Page 975 The frequency is variable between zero and the maximum clock frequency. Refer to ADSP-BF504, ADSP-BF504F, ADSP-BF506F Embedded Processor Data Sheet for maximum sup- ported clock frequencies. • : A bidirectional command signal used for command trans- RSI_CMD fer and card initialization.
Page 976 Interface Overview cards to support open-drain mode. This allows multiple MMC cards to share the data and command signals on the RSI interface and allows for the initialization sequence to take place on all cards. • : These are configurable bidirectional data channels RSI_DATA7-0 used for all data transfers both to and from the card.
Page 977 Removable Storage Interface Table 21-1 Table 21-2 list the RSI interface pins functional opera- tions for all supported protocol modes. Table 21-1. RSI Protocol Interface Signal Name CE-ATA CE-ATA Direction (1-bit) (4-bit) (8-bit) (4-bit) (8-bit) RSI_DATA7 Not Used Not Used Dat7 Not Used Dat7...
Page 978: Description Of Operation
Description of Operation Table 21-2. RSI Protocol Interface Signal Name SDIO SDIO Direction (1-bit) (4-bit) (1-bit) (4-bit) RSI_DATA7 Not Used Not Used Not Used Not Used Bidirectional RSI_DATA6 Not Used Not Used Not Used Not Used Bidirectional RSI_DATA5 Not Used Not Used Not Used Not Used...
Page 979 Removable Storage Interface Communication is via a master and slave type configuration, whereby the RSI is the master and the card is the slave device. The RSI communicates with the device via a message-based bus protocol in which the host sends commands serially via the signal.
Page 980 Description of Operation • Identify the device type, • Assign/request a relative card address (RCA) Only once a device has been assigned an RCA will the device then transi- tion to a stand-by state, where it is then known to be in data transfer mode. Only once the device has entered this mode may data transfers then take place.
Page 981: Functional Description
The following sections describe the functions and features of the RSI controller as well as the MMC, SD, SDIO, and CE-ATA protocols. For detailed information on timing parameters and protocol requirements, refer to ADSP-BF504, ADSP-BF504F, ADSP-BF506F Embedded Processor Data Sheet and the following standards and specifications: •...
Page 982: Rsi Interface Configuration
Functional Description SCLK ---------------------------------------------- - RSI_CLK    CLKDIV output is enabled or disabled via the bit in the RSI_CLK CLK_EN register and a power save feature is implemented via RSI_CLK_CONTROL that allows for the disabling of the output when there PWR_SV_EN RSI_CLK are no transfers taking place on the RSI interface.
Page 983: Card Detection
Removable Storage Interface In order to stop the signals from floating when no card is inserted or dur- ing times when all card drivers are in a high-impedance mode, various pull-up and pull-down resistor configurations can be enabled on the signals.
Page 984 Functional Description Sockets supporting this feature can have the card detect pin de-bounced and connected to a GPIO pin in order to allow not only interrupt-driven card detection but also interrupt-driven card removal. This is the most reliable and efficient method of detecting the insertion and removal of a card as some MMC devices may not implement the card detect pull-up resistor on the signal.
Page 985 Removable Storage Interface 3.3V REQUIRED FOR MMC CARD SUPPORT RSI_CLK RSI_CMD RSI_DATA0 DATA0 RSI_DATA1 DATA1 RSI_DATA2 DATA2 RSI INTERFACE RSI_DATA3 DATA3 SD/MMC SOCKET RSI_DATA4 DATA4 RSI_DATA5 DATA5 RSI_DATA6 DATA6 CARD WRITE RSI_DATA7 DATA7 DETECT PROTECT GPIO GPIO REQUIRED ONLY IF USING CARD DETECTION VIA DATA3 SIGNAL Figure 21-2.
Page 986: Rsi Power Saving Configuration
Functional Description RSI Power Saving Configuration The RSI requires two internal clock signals that are derived directly from . In order for the RSI to function, these clocks must be enabled via SCLK in the register. Clearing disables the RSI_CLK_EN RSI_CONFIG RSI_CLK_EN RSI regardless of the other RSI clock configurations.
Page 987: Rsi Commands And Responses
Removable Storage Interface RSI Commands and Responses The RSI sends commands to and receives responses from the card via the signal. The command to be sent to the card is issued by writing to RSI_CMD register (see “RSI Command Register RSI_COMMAND (RSI_COMMAND)”...
Page 988 Functional Description The RSI can be configured via the fields of the CMD_RESP CMD_L_RESP register to expect the following response types: RSI_COMMAND • No response • Short response (see Table 21-5) • Long response (see Table 21-6) Table 21-5. RSI Short Response Format Bit Position Width Value...
Page 989 Removable Storage Interface Like the commands, all responses are sent on the signal. RSI_CMD A response always has a “0” start bit followed by a “0” transmission bit to indicate the transfer is from card to host. Unlike the commands issued by the host, not all responses are protected by a CRC7 checksum.
Page 990 Functional Description IDLE RSI_CLK_EN && CMD_PEND_EN && CMD_EN RSI_CLK_EN && CMD_EN && !CMD_PEND_EN PEND !RSI_CLK_EN || RSI_RST DAT_END SEND !RSI_CLK_EN || RSI_RST || CMD_SENT CMD_RSP WAIT !RSI_CLK_EN || RSI_RST || CMD_TIMEOUT !CMD_TIMEOUT || (CMD_INT_EN && INTERRUPT REQUEST FROM CARD) RECEIVE !RSI_CLK_EN || RSI_RST || CMD_CRC_FAIL || CMD_RESP_END...
Page 991 Removable Storage Interface Table 21-7 lists the status flags and exception flags that are affected by the command path state machine. Table 21-7. RSI Command Path Status Flags RSI_STATUS Flag Description State Flag Set in Command transfer is in progress WAIT_S CMD_ACT Command without response sent successfully...
Page 992: Idle State
Functional Description IDLE State The command path state machine remains in the IDLE state when not active. The command path state machine becomes enabled and leaves the IDLE state once the bit of the register is set. The state CMD_EN RSI_COMMAND will transition to the PEND state if the bit is set within...
Page 993: Receive State
Removable Storage Interface completion of sending the command depends upon whether the com- mand expects a response back from the card. If no response is expected, the RSI clears the flag and sets the flag to indicate that a CMD_ACT CMD_SENT command operation without a response has been completed and then the state transitions to the IDLE state.
Page 994: Ceata_Int_Dis State
Functional Description flag being set. At this point the state machine then transi- CMD_CRC_FAIL tions to the IDLE state. Some CE-ATA commands require additional functionality upon reaching this state. This additional functionality requires sending a command completion signal back to the host upon completion of a specific task. For commands that require this functionality, the CEATA_EN bits of the...
Page 995: Rsi Command Path Crc
Removable Storage Interface RSI Command Path CRC The command CRC generator of the RSI calculates the 7-bit CRC check- sum for all 40 bits preceding the CRC code for both 48-bit commands and 48-bit responses. This includes the start bit, transmitter bit, com- mand index, and command argument (or card status).
Page 996 Functional Description Register (RSI_CLK_CONTROL)” on page 21-55). The default configu- ration is for 1-bit bus mode, whereby the data is transferred over the signal. Alternatively, 4-bit mode or 8-bit mode may be enabled RSI_DATA0 after configuring the card for 4-bit or 8-bit mode of operation, respec- tively.
Page 997 Removable Storage Interface Table 21-8. RSI_STATUS Flags RSI_STATUS Flag Description States Flag Set in TX_ACT Data transmit in progress WAIT_S RX_ACT Data receive in progress WAIT_R DAT_BLK_END Data block sent successfully and BUSY CRC pass token received (block transfer mode only) Data block received correctly RECEIVE and CRC passed...
Page 998: Rsi Data Transmit Path
Functional Description Table 21-8. RSI_STATUS Flags (Cont’d) RSI_STATUS Flag Description States Flag Set in RX_ OVERRUN Receive FIFO over run error RECEIVE RX_FIFO_RDY Valid data is available in the RECEIVE receive FIFO RSI Data Transmit Path The transmit path consists of the WAIT_S, SEND, and BUSY states. Before enabling the data path state machine via , both RSI_DATA_CONTROL...
Page 999: Rsi Data Receive Path
Removable Storage Interface the total number of bytes transmitted for the current block results in the decrementing to zero and the number of bytes transferred is RSI_DATA_CNT not equal to , the transmission stops and the DATA_BLK_LGTH DAT_CRC_FAIL flag is set and the data path returns to the IDLE state. If at any point dur- ing the block transfer the transmit FIFO becomes empty and data is not available in the FIFO by the time the next transfer is due to take place, the flag is set before returning to the IDLE state.
Page 1000 Functional Description timeout counter expiring, the flag is set and the state DAT_TIMEOUT machine returns to the IDLE state. If the RSI is configured for 4-bit bus mode and a start bit is detected on some of the signals but not RSI_DATAx all of them on the same sampled clock cycle, the flag is set...

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