Analog Devices ADSP-BF506F Hardware Reference Manual page 555

Controller is t
SCLK
the fundamental time increment (t
register is effectively the number of t
PWM_TM
a PWM period. The required
PWM switching frequency (f
Therefore, the PWM switching period (T
For example, for an f
quency (f ) of 10 kHz (T
PWM
register is:
PWM_TM
The largest value that can be written to the 16-bit
0xFFFF = 65,535, which, at an f
imum PWM switching frequency of:

PWM_TM
when the PWM outputs or PWM sync is enabled.
ADSP-BF50x Blackfin Processor Hardware Reference
. Therefore, for a 100 MHz system clock (
PWM_TM
PWM
PWM_TM

=
T 2 PWM_TM
S
of 100 MHz and a desired PWM switching fre-
SCLK
= 100
s
100 10
= ----------------------------- -
PWM_TM

2 10
100 10
= ----------------------- -
f
 
PWM min
2 65535
values of 0 and 1 are not defined and should not be used
) is 10 ns. The value written to the
SCLK
clock increments in half
SCLK
value as a function of the desired
) is given by:
f
SCLK
= ------------------------

2 f
PWM
) can be written as:
s

t
SCLK

s), the correct value to load into the
6

=
5000
3

10
PWM_TM
of 100 MHz, corresponds to a min-
SCLK
6

=
762Hz

PWM Controller
), f ,
SCLK
SCLK
register is
14-11