Dma Transmit And Mdma Source - Analog Devices ADSP-BF506F Hardware Reference Manual

Functional Description
0. In transmit (memory read) channels, the
descriptor prior to the transition controls the transition behavior.
In contrast, in receive channels, the
of the next descriptor chain controls the transition.

DMA Transmit and MDMA Source

In DMA transmit (memory read) and MDMA source channels, the
bit controls the interrupt timing at the end of the work unit and the han-
dling of the DMA FIFO between the current and next work units.
If = 0, a continuous transition is selected. In a continuous transition,
SYNC
just after the last data item is read from memory, the following operations
start in parallel:
• The interrupt (if any) is signalled.
• The
DMA_DONE
• The next descriptor begins to be fetched.
• The final data items are delivered from the DMA FIFO to the des-
tination memory or peripheral.
This allows the DMA to provide data from the FIFO to the peripheral
"continuously" during the descriptor fetch latency period.
When = 0, the final interrupt (if enabled) occurs when the last data is
SYNC
read from memory. This interrupt is at the earliest time that the output
memory buffer may safely be modified without affecting the previous data
transmission. Up to four data items may still be in the DMA FIFO,
however, and not yet at the peripheral, so the DMA interrupt should not
be used as the sole means of synchronizing the shutdown or reconfigura-
tion of the peripheral following a transmission.
7-26
bit in the
DMAx_IRQ_STATUS
ADSP-BF50x Blackfin Processor Hardware Reference
bit of the last
SYNC
bit of the first descriptor
SYNC
register is set.
SYNC