Analog Devices ADSP-BF506F Hardware Reference Manual page 960

PPI Registers
PPI Control Register (PPI_CONTROL)
15 14 13 12 11 10
0
POLS
0 - PPI_FS1 and
PPI_FS2 are treated
as rising edge
asserted
1 - PPI_FS1 and
PPI_FS2 are treated
as falling edge
asserted
POLC
0 - PPI samples data on rising
edge and drives data on
falling edge of PPI_CLK
1 - PPI samples data on falling
edge and drives data on
rising edge of PPI_CLK
DLEN[2:0] (Data Length)
000 - 8 bits
001 - 10 bits
010 - 11 bits
011 - 12 bits
100 - 13 bits
101 - 14 bits
110 - 15 bits
111 - 16 bits
SKIP_EO (Skip Even Odd)
In ITU-R 656 and GP Input modes:
0 - Skip odd-numbered elements
1 - Skip even-numbered elements
SKIP_EN (Skip Enable)
In ITU-R 656 and GP Input modes:
0 - Skipping disabled
1 - Skipping enabled
PACK_EN (Packing Mode Enable)
0 - Disabled
1 - Output mode, unpacking enabled;
Input mode, packing enabled
FLD_SEL (Active Field Select)
In ITU-R 656 modes, when XFR_TYPE = 00:
0 - Field 1
1 - Fields 1 and 2
In RX mode with external frame sync, when PORT_CFG = 11:
0 - External trigger
1 - Internal trigger
Figure 20-13. PPI Control Register
20-26
9 8 7
0 0 0 0 0 0 0 0
ADSP-BF50x Blackfin Processor Hardware Reference
6 5 4 3 2 1 0
0 0 0 0 0 0 0
PORT_EN (Enable)
0 - PPI disabled
1 - PPI enabled
PORT_DIR (Direction)
0 - PPI in Receive mode (input)
1 - PPI in Transmit mode
XFR_TYPE[1:0] (Transfer
Type)
In Input mode:
00 - ITU-R 656, Active Field Only
01 - ITU-R 656, Entire Field
10 - ITU-R 656, Vertical Blanking
11 - Non-ITU-R 656 mode
In Output mode:
00, 01, 10 - Sync-less Output
11 - Output mode with 1, 2, or
PORT_CFG[1:0] (Port
Configuration)
In non-ITU-R 656 Input modes
(PORT_DIR = 0, XFR_TYPE = 11):
00 - 1 external frame sync
01 - 2 or 3 internal frame syncs
10 - 2 or 3 external frame syncs
11 - 0 frame syncs, triggered
In Output modes with frame syncs
(PORT_DIR = 1, XFR_TYPE = 11):
00 - 1 frame sync
01 - 2 or 3 frame syncs
10 - Reserved
11 - Sync PPI_FS3 to assertion of
Reset = 0x0000
(output)
Only
mode
3 frame syncs
PPI_FS2 rather than of
PPI_FS1.