Mixing Modes - Analog Devices ADSP-BF506F Hardware Reference Manual

the control bit only when the
ETBEI
data bytes might be lost.
When the
ETBEI
DMA request is issued immediately. It is common practice to clear the
bit by the DMA's service routine.
ETBEI
In DMA transmit mode, the
the DMA FIFO. The strobe on the memory side is still enabled by the
bit. If the DMA count is less than the DMA FIFO depth, which is
DMAEN
4, then the DMA interrupt might be requested already before the
bit is set. If this is not wanted, set the
Regardless of the
transmitter completely at the time the interrupt is generated. Transmis-
sion may abort in the middle of the stream, causing data loss, if the UART
clock was disabled without additional synchronization with the
The UART's DMA supports 8-bit and 16-bit operation, but not 32-bit
operation. Sign extension is not supported.

Mixing Modes

Especially on the transmit side, switching from DMA mode to non-DMA
operation on the fly requires some thought. By default, the interrupt tim-
ing of the DMA is synchronized with the memory side of the DMA
FIFOs. Normally, the UARTxTX DMA completion interrupt is generated
after the last byte is copied from the memory into the DMA FIFO. The
UARTxTX DMA interrupt service routine is not yet permitted to disable
the DMA enable bit
bit is set. The
DMA_DONE
has completely left the UARTxTX DMA FIFO.
Therefore, when planning to switch from DMA to non-DMA of opera-
tion, always set the
or work unit before handing over control to non-DMA mode. Then, after
ADSP-BF50x Blackfin Processor Hardware Reference
bit is set in the
UARTx_IER_SET
ETBEI
setting, the DMA stream has not left the UART
SYNC
. The interrupt is requested by the time the
DMAEN
bit, however, remains set until the data
DMA_RUN
bit in the
SYNC DMAx_CONFIG
UART Port Controllers
bit is set, otherwise up to four
SYNC
register, an initial transmit
bit enables the peripheral request to
bit in the
SYNC DMAx_CONFIG
word of the last descriptor
ETBEI
register.
bit.
TEMT
15-25