Analog Devices ADSP-BF59x Blackfin Manuals

Manuals and User Guides for Analog Devices ADSP-BF59x Blackfin. We have 1 Analog Devices ADSP-BF59x Blackfin manual available for free PDF download: Hardware Reference Manual

Analog Devices ADSP-BF59x Blackfin Hardware Reference Manual

Analog Devices ADSP-BF59x Blackfin Hardware Reference Manual (772 pages)

Brand: Analog Devices | Category: Processor | Size: 5 MB

Table of Contents

Hardware Reference
1
Copyright Information
2
Table of Contents
3
Preface

33
- Purpose of this Manual
  33
- Intended Audience
  33
- Manual Contents
  34
- What's New in this Manual
  36
- Technical or Customer Support
  36
  - Registration for Myanalog.com
    37
  - Engineerzone
    37
  - Social Networking Web Sites
    38
- Supported Processors
  38
- Product Information
  39
- Notation Conventions
  41
Introduction

43
- General Description of Processor
  43
  - Portable Low-Power Architecture
    44
- Peripherals
  45
- Memory Architecture
  46
  - Internal Memory
    47
  - I/O Memory Space
    47
- DMA Support
  48
- General-Purpose I/O (GPIO)
  49
- Two-Wire Interface
  50
- Parallel Peripheral Interface
  51
- SPORT Controllers
  53
- Serial Peripheral Interface (SPI) Ports
  55
- Timers
  55
- UART Port
  56
- Watchdog Timer
  57
- Clock Signals
  58
- Dynamic Power Management
  58
- Instruction Set Description
  60
- Development Tools
  61
Memory

65
- Memory Architecture
  65
- L1 Instruction SRAM
  66
- L1 Instruction ROM
  67
- L1 Data SRAM
  67
- Boot ROM
  68
- External Memory
  68
- Processor-Specific Mmrs
  68
  - DTEST_COMMAND Register
    69
  - ITEST_COMMAND Register
    70
  - DMEM_CONTROL Register
    71
  - IMEM_CONTROL Register
    71
  - Dcplb_Datax Registers
    72
  - Icplb_Datax Registers
    73
Chip Bus Hierarchy

75
- Chip Bus Hierarchy Overview
  75
- Interface Overview
  76
  - Internal Clocks
    77
  - Core Bus Overview
    77
  - Peripheral Access Bus (PAB)
    78
    
    PAB Agents (Masters, Slaves)
    79
    
    PAB Arbitration
    79
    
    PAB Performance
    80
  - DMA Access Bus (DAB), DMA Core Bus (DCB)
    80
    
    DAB and DCB Arbitration
    80
    
    DAB Bus Agents (Masters)
    81
    
    DAB and DCB Performance
    82
System Interrupts

83
Direct Memory Access

101
- Specific Information for the ADSP-Bf59X
  101
- Overview and Features
  102
- DMA Controller Overview
  104
  - External Interfaces
    104
  - Internal Interfaces
    104
  - Peripheral DMA
    105
  - Memory DMA
    106
    
    Handshaked Memory DMA (HMDMA) Mode
    108
- Modes of Operation
  109
  - Register-Based DMA Operation
    109
    
    Autobuffer Mode
    111
    
    Stop Mode
    111
  - Two-Dimensional DMA Operation
    111
    
    Examples of Two-Dimensional DMA
    112
  - Descriptor-Based DMA Operation
    113
    
    Descriptor List Mode
    114
    
    Descriptor Array Mode
    115
    
    Variable Descriptor Size
    115
    
    Mixing Flow Modes
    116
- Functional Description
  117
  - DMA Operation Flow
    117
    
    DMA Startup
    117
    
    DMA Refresh
    122
  - Work Unit Transitions
    124
    
    DMA Transmit and MDMA Source
    125
    
    DMA Receive
    126
  - Stopping DMA Transfers
    128
- DMA Errors (Aborts)
  128
- DMA Control Commands
  131
  - Restrictions
    134
    
    Transmit Restart or Finish
    134
    
    Receive Restart or Finish
    135
- Handshaked Memory DMA Operation
  136
  - Pipelining DMA Requests
    137
  - HMDMA Interrupts
    139
- DMA Performance
  140
  - DMA Throughput
    141
  - Memory DMA Timing Details
    144
  - Static Channel Prioritization
    144
  - Temporary DMA Urgency
    144
  - Memory DMA Priority and Scheduling
    146
  - Traffic Control
    148
- Programming Model
  150
- Programming Examples
  190
Dynamic Power Management

205
- Phase Locked Loop and Clock Control
  205
  - PLL Overview
    206
  - PLL Clock Multiplier Ratios
    207
    
    Core Clock/System Clock Ratio Control
    209
- Dynamic Power Management Controller
  211
  - Operating Modes
    211
  - Dynamic Power Management Controller States
    212
    
    Active Mode
    212
    
    Full-On Mode
    212
    
    Deep Sleep Mode
    213
    
    Sleep Mode
    213
    
    Hibernate State
    214
  - Operating Mode Transitions
    214
  - Programming Operating Mode Transitions
    217
  - Dynamic Supply Voltage Control
    219
  - Power Supply Management
    219
    
    Changing Voltage
    219
    
    Powering down the Core (Hibernate State)
    221
- PLL and VR Registers
  222
  - PLL_DIV Register
    223
  - PLL_CTL Register
    224
  - PLL_STAT Register
    224
  - PLL_LOCKCNT Register
    225
  - VR_CTL Register
    225
- System Control ROM Function
  226
- Programming Examples
  232
General-Purpose Ports

245
- Overview
  245
- Features
  245
- Interface Overview
  246
  - External Interface
    247
    
    Port F Structure
    247
    
    Port G Structure
    248
    
    Additional Considerations
    249
  - Internal Interfaces
    250
  - Performance/Throughput
    250
- Description of Operation
  251
  - Operation
    251
  - General-Purpose I/O Modules
    252
  - GPIO Interrupt Processing
    255
- Programming Model
  261
- GPIO Schmitt Trigger Control
  263
  - Portx Pad Control Registers
    263
- Memory-Mapped GPIO Registers
  264
- Programming Examples
  277
General-Purpose Timers

279
- Specific Information for the ADSP-Bf59X
  279
- Overview
  280
  - External Interface
    281
  - Internal Interface
    282
- Description of Operation
  282
  - Interrupt Processing
    283
  - Illegal States
    285
- Modes of Operation
  288
  - Pulse Width Modulation (PWM_OUT) Mode
    288
    
    Output Pad Disable
    290
    
    Single Pulse Generation
    290
    
    Pulse Width Modulation Waveform Generation
    291
    
    PULSE_HI Toggle Mode
    293
    
    Externally Clocked PWM_OUT
    298
    
    Stopping the Timer in PWM_OUT Mode
    299
    
    Using PWM_OUT Mode with the PPI
    299
  - Pulse Width Count and Capture (WDTH_CAP) Mode
    301
    
    Autobaud Mode
    309
  - External Event (EXT_CLK) Mode
    310
- Programming Model
  311
- Timer Registers
  312
- Programming Examples
  326
- Unique Information for the ADSP-Bf59X Processor
  334
  - Interface Overview
    335
    
    External Interface
    336
Core Timer

337
- Specific Information for the ADSP-Bf59X
  337
- Overview and Features
  337
- Timer Overview
  338
  - Internal Interfaces
    339
- Description of Operation
  339
  - Interrupt Processing
    339
- Core Timer Registers
  340
- Programming Examples
  343
- Unique Information for the ADSP-Bf59X Processor
  345
10 Watchdog Timer

347
- Specific Information for the ADSP-Bf59X
  347
- Overview and Features
  347
- Interface Overview
  349
  - External Interface
    349
  - Internal Interface
    349
- Description of Operation
  350
- Register Definitions
  351
- Programming Examples
  354
- Unique Information for the ADSP-Bf59X Processor
  356
11 Uart Port Controllers

357
- Specific Information for the ADSP-Bf59X
  357
- Overview
  358
- Features
  358
- Interface Overview
  359
  - External Interface
    359
  - Internal Interface
    360
- Description of Operation
  361
  - UART Transfer Protocol
    361
  - UART Transmit Operation
    362
  - UART Receive Operation
    363
  - Irda Transmit Operation
    364
  - Irda Receive Operation
    365
  - Interrupt Processing
    367
  - Bit Rate Generation
    368
  - Autobaud Detection
    369
- Programming Model
  371
  - Non-DMA Mode
    371
  - DMA Mode
    373
  - Mixing Modes
    374
- UART Registers
  375
- Programming Examples
  388
- Unique Information for the ADSP-Bf59X Processor
  397
Two Wire Interface Controller

399
- Overview
  400
- Interface Overview
  401
  - External Interface
    402
    
    Serial Clock Signal (SCL)
    402
    
    Serial Data Signal (SDA)
    402
    
    TWI Pins
    403
  - Internal Interfaces
    403
- Description of Operation
  404
  - TWI Transfer Protocols
    404
    
    Clock Generation and Synchronization
    405
    
    Bus Arbitration
    406
    
    Start and Stop Conditions
    406
    
    General Call Support
    407
    
    Fast Mode
    408
- Functional Description
  408
  - General Setup
    408
  - Slave Mode
    409
  - Master Mode Clock Setup
    410
  - Master Mode Transmit
    410
  - Master Mode Receive
    412
    
    Repeated Start Condition
    413
    
    Transmit/Receive Repeated Start Sequence
    413
    
    Receive/Transmit Repeated Start Sequence
    414
    
    Clock Stretching
    415
    
    Clock Stretching During FIFO Underflow
    415
    
    Clock Stretching During FIFO Overflow
    417
    
    Clock Stretching During Repeated Start Condition
    418
- Programming Model
  420
- Register Descriptions
  422
- Programming Examples
  444
  - Master Mode Setup
    444
  - Slave Mode Setup
    448
- Electrical Specifications
  454
- Unique Information for the ADSP-Bf59X Processor
  454
Spi-Compatible Port Controller

455
- Specific Information for the ADSP-Bf59X
  455
- Overview
  456
- Features
  456
- Interface Overview
  457
  - External Interface
    458
    
    SPI Clock Signal (SCK)
    458
    
    Master-In, Slave-Out (MISO) Signal
    459
    
    Master-Out, Slave-In (MOSI) Signal
    459
    
    SPI Slave Select Enable Output Signals
    460
    
    SPI Slave Select Input Signal (SPISS)
    460
    
    Slave Select Inputs
    461
    
    Use of FLS Bits in SPI_FLG for Multiple Slave SPI Systems
    462
  - Internal Interfaces
    464
    
    DMA Functionality
    464
- Description of Operation
  465
  - SPI Transfer Protocols
    465
  - SPI General Operation
    468
  - Clock Signals
    469
  - Interrupt Output
    470
- Functional Description
  470
- Programming Model
  475
  - Beginning and Ending an SPI Transfer
    475
  - Master Mode DMA Operation
    477
  - Slave Mode DMA Operation
    480
- SPI Registers
  487
  - SPI Baud Rate (SPI_BAUD) Register
    488
  - SPI Control (SPI_CTL) Register
    489
  - SPI Flag (SPI_FLG) Register
    491
  - SPI Status (SPI_STAT) Register
    492
    
    Mode Fault Error (MODF)
    493
    
    Transmission Error (TXE)
    494
    
    Reception Error (RBSY)
    495
    
    Transmit Collision Error (TXCOL)
    495
  - SPI Transmit Data Buffer (SPI_TDBR) Register
    495
  - SPI Receive Data Buffer (SPI_RDBR) Register
    496
  - SPI RDBR Shadow (SPI_SHADOW) Register
    497
- Programming Examples
  497
  - Core-Generated Transfer
    497
    
    Initialization Sequence
    498
    
    Starting a Transfer
    499
    
    Post Transfer and Next Transfer
    500
    
    Stopping
    500
  - DMA-Based Transfer
    501
    
    DMA Initialization Sequence
    501
    
    SPI Initialization Sequence
    502
    
    Starting a Transfer
    503
    
    Stopping a Transfer
    504
- Unique Information for the ADSP-Bf59X Processor
  506
14 Sport Controller

507
- Specific Information for the ADSP-Bf59X
  507
- Overview
  508
  - Features
    508
- Interface Overview
  510
  - SPORT Pin/Line Terminations
    514
- Description of Operation
  515
  - SPORT Disable
    515
  - Setting SPORT Modes
    516
  - Stereo Serial Operation
    516
  - Multichannel Operation
    520
    
    Multichannel Enable
    523
    
    Frame Syncs in Multichannel Mode
    524
    
    The Multichannel Frame
    525
    
    Multichannel Frame Delay
    526
    
    Window Size
    526
    
    Other Multichannel Fields in SPORT_MCMC2
    527
    
    Window Offset
    527
    
    Channel Selection Register
    528
    
    Multichannel DMA Data Packing
    529
  - Support for H.100 Standard Protocol
    530
    
    2× Clock Recovery Control
    530
- Functional Description
  531
  - Clock and Frame Sync Frequencies
    531
  - Maximum Clock Rate Restrictions
    532
- Word Length
  533
- Bit Order
  533
- Data Type
  533
- Companding
  534
- Clock Signal Options
  535
- Frame Sync Options
  536
- Moving Data between Sports and Memory
  543
- SPORT RX, TX, and Error Interrupts
  543
- Peripheral Bus Errors
  544
- Timing Examples
  544
- SPORT Registers
  550
Parallel Peripheral Interface

585
- Specific Information for the ADSP-Bf59X
  585
- Overview
  586
- Features
  586
- Interface Overview
  587
- Description of Operation
  588
- Functional Description
  589
  - ITU-R 656 Modes
    589
    
    ITU-R 656 Background
    589
    
    Entire Field
    593
    
    ITU-R 656 Input Modes
    593
    
    Active Video Only
    594
    
    Vertical Blanking Interval (VBI) Only
    594
    
    Frame Synchronization in ITU-R 656 Modes
    595
    
    ITU-R 656 Output Mode
    595
  - General-Purpose PPI Modes
    596
    
    Data Input (RX) Modes
    598
    
    No Frame Syncs
    598
    
    1, 2, or 3 External Frame Syncs
    599
    
    Data Output (TX) Modes
    600
    
    Or 3 Internal Frame Syncs
    600
    
    No Frame Syncs
    601
    
    Or 2 External Frame Syncs
    601
    
    1, 2, or 3 Internal Frame Syncs
    602
    
    Frame Synchronization in GP Modes
    603
    
    Modes with Internal Frame Syncs
    603
    
    Modes with External Frame Syncs
    604
- Programming Model
  605
  - DMA Operation
    606
- PPI Registers
  609
- Programming Examples
  618
- Unique Information for the ADSP-Bf59X Processor
  621
System Reset and Booting

623
- Overview
  623
- Reset and Power-Up
  625
  - Hardware Reset
    626
  - Software Resets
    627
  - Reset Vector
    628
  - Servicing Reset Interrupts
    628
- Basic Booting Process
  630
  - Block Headers
    632
    
    Block Code
    634
    
    Block Flags Field
    636
    
    Header Checksum Field
    637
  - Target Address
    638
    
    Header Sign Field
    638
  - Byte Count
    639
  - Argument
    639
- Boot Host Wait (HWAIT) Feedback Strobe
  640
- Boot Termination
  641
  - Using HWAIT as Reset Indicator
    641
- Single Block Boot Streams
  642
- Advanced Boot Techniques
  643
  - Quick Boot
    647
  - Indirect Booting
    648
  - Callback Routines
    649
  - Error Handler
    652
  - CRC Checksum Calculation
    652
  - Load Functions
    652
  - Calling the Boot Kernel at Runtime
    654
  - Debugging the Boot Process
    654
- Boot Management
  657
  - Multi-DXE Boot Streams
    658
    
    Determining Boot Stream Start Addresses
    659
  - Specific Boot Modes
    660
    
    Initialization Hook Routine
    660
    
    No Boot Mode
    661
    
    SPI Master Boot Modes
    662
    
    SPI Device Detection Routine
    664
    
    SPI Slave Boot Mode
    666
    
    PPI Boot Mode
    669
    
    UART Slave Mode Boot
    671
  - Reset and Booting Registers
    673
    
    L1 ROM Boot Mode
    673
    
    Software Reset (SWRST) Register
    674
    
    System Reset Configuration (SYSCR) Register
    676
    
    Boot Code Revision Control (BK_REVISION)
    677
    
    Boot Code Date Code (BK_DATECODE)
    678
    
    Zero Word (BK_ZEROS)
    679
  - Data Structures
    680
    
    Adi_Boot_Data
    681
    
    Adi_Boot_Header
    681
    
    Dflags Word
    685
  - Callable ROM Functions for Booting
    686
    
    Bfrom_Finalinit
    686
    
    Bfrom_Mdma
    687
    
    Bfrom_Pdma
    687
    
    Bfrom_Spiboot
    688
    
    Bfrom_Bootkernel
    690
    
    Bfrom_Crc32
    690
    
    Bfrom_Crc32Poly
    691
    
    Bfrom_Crc32Callback
    692
    
    Bfrom_Crc32Initcode
    692
  - Programming Examples
    693
    
    System Reset
    693
    
    Exiting Reset to Supervisor Mode
    694
    
    Exiting Reset to User Mode
    694
    
    Initcode (Power Management Control)
    695
    
    XOR Checksum
    697
17 System Design

701
- Pin Descriptions
  701
- Configuring and Servicing Interrupts
  702
- Data Delays, Latencies and Throughput
  702
  - Managing Core and System Clocks
    702
- Bus Priorities
  703
- High-Frequency Design Considerations
  703
  - Signal Integrity
    703
  - Decoupling Capacitors and Ground Planes
    704
  - Oscilloscope Probes
    706
  - Test Point Access
    706
  - Recommended Reading
    707
- Resetting the Processor
  708
- Recommendations for Unused Pins
  708
- Programmable Outputs
  709
- Voltage Regulation Interface
  709
System Mmr Assignments

711
- Processor-Specific Memory Registers
  712
- Core Timer Registers
  713
- System Reset and Interrupt Control Registers
  713
- Dma/Memory DMA Control Registers
  714
- Ports Registers
  717
- Timer Registers
  719
- Watchdog Timer Registers
  721
- Dynamic Power Management Registers
  721
- PPI Registers
  722
- SPI Controller Registers
  722
- SPORT Controller Registers
  724
- SPORT Clock Gating Register
  727
- UART Controller Registers
  728
- TWI Registers
  729
Test Features

731
- JTAG Standard
  731
- Boundary-Scan Architecture
  732
  - Instruction Register
    734
  - Public Instructions
    735
    
    BYPASS - Binary Code 11111
    736
    
    EXTEST - Binary Code 00000
    736
    
    SAMPLE/PRELOAD - Binary Code 10000
    736
  - Boundary-Scan Register
    737
Index

739

Advertisement

Advertisement

Related Products

Analog Devices Categories

Motherboard Computer Hardware Controller Media Converter Extender

More Analog Devices Manuals