Memory Dma - Analog Devices ADSP-BF506F Hardware Reference Manual

DMA Controller Overview
The default configuration should suffice in most cases, but there are some
cases where remapping the assignment can be helpful because of the DMA
channel priorities. When competing for any of the system buses, DMA0
has higher priority than DMA1, and so on. DMA11 has the lowest prior-
ity of the peripheral DMA channels.

A 1:1 mapping should exist between DMA channels and peripher-
als. The user is responsible for ensuring that multiple DMA
channels are not mapped to the same peripheral and that multiple
peripherals are not mapped to the same DMA port. If multiple
channels are mapped to the same peripheral, only one channel is
connected (the lowest priority channel). If a nonexistent peripheral
(for example, 0xF in the
channel is disabled—DMA requests are ignored, and no DMA
grants are issued. The DMA requests are also not forwarded from
the peripheral to the interrupt controller.
All peripheral DMA channels work completely independently from each
other. The transfer timing is controlled by the mapped peripheral.
Every DMA channel features its own 4-deep FIFO that decouples DAB
activity from DCB and DEB availability. DMA interrupt and descriptor
fetch timing is aligned with the memory side (DCB/DEB side) of the
FIFO. The user does, however, have an option to align interrupts with the
peripheral side (DAB side) of the FIFO for transmit operations. Refer to
the bit in the
SYNC

Memory DMA

This section describes the two pairs of MDMA channels, which provide
memory-to-memory DMA transfers among the various memory spaces.
These include L1 memory and external synchronous/asynchronous
memories.
Each MDMA channel contains a DMA FIFO, an 8-word by 16-bit FIFO
block used to transfer data to and from either L1 or the DCB and DEB
7-6
PMAP
register for details.
DMAx_CONFIG
ADSP-BF50x Blackfin Processor Hardware Reference
field) is mapped to a channel, that