Memory Dma Timing Details; Static Channel Prioritization; Temporary Dma Urgency - Analog Devices ADSP-BF506F Hardware Reference Manual

DMA in s (which is typically seven for internal transfers and six for
SCLK
external transfers).

Memory DMA Timing Details

When the destination
starts after a latency of three
If either MDMA channel has been selected to use descriptors, the descrip-
tors are fetched from memory. The destination channel descriptors are
fetched first. Then the source MDMA channel begins fetching data from
the source buffer, after a latency of four
tor word is returned from memory. Due to memory pipelining, this is
typically eight
resulting data is deposited in the MDMA channel's 8-location FIFO.
After a latency of two
writing data to the destination memory buffer.

Static Channel Prioritization

DMA channels are ordinarily granted service strictly according to their
priority. The priority of a channel is simply its channel number, where
lower priority numbers are granted first. Thus, peripherals with high data
rates or low latency requirements should be assigned to lower numbered
(higher priority) channels using the
DMAx_PERIPHERAL_MAP
lower static priority than the peripherals, but as they request service con-
tinuously, they ensure that any time slots unused by peripheral DMA are
applied to MDMA transfers.

Temporary DMA Urgency

Typically, DMA transfers for a given peripheral occur at regular intervals.
Generally, the shorter the interval, the higher the priority that should be
assigned to the peripheral. If the average bandwidth of all the peripherals
ADSP-BF50x Blackfin Processor Hardware Reference
DMAx_CONFIG
SCLK
cycles after the fetch of the last descriptor word. The
SCLK
cycles, the destination MDMA channel begins
SCLK
registers. The memory DMA streams are always
Direct Memory Access
register is written, MDMA operation
cycles.
cycles after the last descrip-
SCLK
field in the
PMAP
7-45