Analog Devices ADSP-BF506F Hardware Reference Manual page 929

W[P0 + (SPORT0_TCR2 - SPORT0_TCR1)] = R1;
/* Configuration register 1
nally generated clk and framesync) */
R1 = SPORT_TRANSMIT_CONF_1;
W[P0] = R1;
ssync;
/* NOTE: SPORT0 TX NOT enabled yet (bit 0 of TCR1 must be zero) */
Program_SPORT_RECEIVER_Registers:
/* Set P0 to SPORT0 Base Address */
P0.h = hi(SPORT0_RCR1);
P0.l = lo(SPORT0_RCR1);
/* Configure Clock speeds */
R1 = SPORT_RCLK_CONFIG;
65535) */
W[P0 + (SPORT0_RCLKDIV - SPORT0_RCR1)] = R1;
register */
/* number of Bitclock between FrameSyncs -1
to 65535) */
R1 = SPORT_RFSDIV_CONFIG;
W[P0 + (SPORT0_RFSDIV - SPORT0_RCR1)] = R1;
/* Receive configuration */
/* Configuration register 2
wordlength) */
R1 = SPORT_RECEIVE_CONF_2;
W[P0 + (SPORT0_RCR2 - SPORT0_RCR1)] = R1;
/* Configuration register 1
clk and framesync) */
R1 = SPORT_RECEIVE_CONF_1;
ADSP-BF50x Blackfin Processor Hardware Reference
(for instance 0x4E12 for inter-
/* Divider SCLK/RCLK (value 0 to
/* RFSDIV register */
(for instance 0x000E for 16-bit
(for instance 0x4410 for external
SPORT Controller
/* RCK divider
(value SPORT_SLEN
19-71