Dynamic Power Management; Full-On Operating Mode-Maximum Performance; Active Operating Mode-Moderate Dynamic Power Savings - Analog Devices ADSP-BF506F Hardware Reference Manual

Dynamic Power Management

64×) multiplication factor (bounded by specified minimum and maxi-
mum frequencies). The default multiplier is 6×, but it can be modified
VCO
by a software instruction sequence. On-the-fly frequency changes can be
made by simply writing to the
All on-chip peripherals are clocked by the system clock (
clock frequency is programmable by means of the
register.
PLL_DIV
Dynamic Power Management
The processor provides five operating modes, each with a different perfor-
mance/power profile. In addition, dynamic power management provides
the control functions to dynamically alter the processor core supply volt-
age, further reducing power dissipation. When configured for a 0 volt core
supply voltage, the processor enters the hibernate state. Control of clock-
ing to each of the processor peripherals also reduces power consumption.
See Table 1-3
Full-On Operating Mode—Maximum Performance
In the full-on mode, the PLL is enabled and is not bypassed, providing
capability for maximum operational frequency. This is the power-up
default execution state in which maximum performance can be achieved.
The processor core and all enabled peripherals run at full speed.
Active Operating Mode—Moderate Dynamic
Power Savings
In the active mode, the PLL is enabled but bypassed. Because the PLL is
bypassed, the processor's core clock (CCLK) and system clock (SCLK) run
at the input clock (CLKIN) frequency. DMA access is available to appro-
priately configured L1 memories.
1-24
PLL_DIV
for a summary of the power settings for each mode.
ADSP-BF50x Blackfin Processor Hardware Reference
register.
SCLK
SSEL[3:0]
). The system
bits of the