Analog Devices ADSP-BF506F Hardware Reference Manual page 736

Functional Operation
status bits in the global CAN interrupt status register, however, are always
set if the corresponding interrupt event occurs, independent of the mask
bits. Thus, the interrupt status bits can be used for polling of interrupt
events.
The global CAN status interrupt output (
interrupt status register is only asserted if a bit in the
set. The bit remains set as long as at least one bit in the interrupt flag
GIRQ
register
CAN_GIF
flag registers remain set until cleared by software or a software reset has
occurred.

In the ISR, the interrupt latch should be cleared by a W1C opera-
tion to the corresponding bit of the
the related bits of both the
There are several interrupt events that can activate this
• Access denied interrupt (
At least one access to the mailbox RAM occurred during a data
update by internal logic.
• External trigger output interrupt (
The external trigger event occurred.
• Universal counter exceeded interrupt (
There was an overflow of the universal counter (in time stamp
mode or event counter mode) or the counter has reached the value
0x0000 (in watchdog mode).
• Receive message lost interrupt (
A message has been received for a mailbox that currently contains
unread data. At least one bit in the receive message lost register
(
CAN_RMLx
17-24
is set. All bits in the interrupt status and in the interrupt
CAN_GIS
ADIM
) is set. If the bit in
ADSP-BF50x Blackfin Processor Hardware Reference
) bit in the global CAN
GIRQ
CAN_GIF
register. This clears
CAN_GIS
and
CAN_GIF
, , )
ADIS ADIF
, ,
EXTIM EXTIS
,
UCEIM UCEIS
, ,
RMLIM RMLIS RMLIF
(and
CAN_GIS CAN_GIF
register is
registers.
interrupt:
GIRQ
)
EXTIF
, )
UCEIF
)
) is reset and