Sport Receive Data (Sport_Rx) Register - Analog Devices ADSP-BF506F Hardware Reference Manual

SPORT Transmit Data Register (SPORT_TX)
31 30 29 28 27 26
0 0 0 0 0
15 14 13 12 11 10
0 0 0 0 0
Figure 19-30. SPORT Transmit Data Register

SPORT Receive Data (SPORT_RX) Register

The
SPORT_RX
bus error. The same location is read for both primary and secondary data.
Reading from this register space causes reading of the receive FIFO. This
16-bit FIFO is 8 deep for receive word length
length > 16 bits. The FIFO is shared by both primary and secondary
receive data. The order for reading using peripheral bus/DMA reads is
important since data is stored in differently depending on the setting of
the and
SLEN RXSE
Data storage and data ordering in the FIFO are shown in
The
SPORT_RX
ADSP-BF50x Blackfin Processor Hardware Reference
25 24 23 22 21 20 19 18 17 16
0 0 0 0 0 0 0 0
9 8 7 6 5 4 3
0 0 0 0 0 0 0 0
register is a read-only register. Writes produce a peripheral
configuration bits.
register is shown in
0 0 0 Reset = 0x0000 0000
Transmit Data[31:16]
2 1 0
0 0 0
Transmit Data[15:0]

16 and 4 deep for
Figure 19-32.
SPORT Controller
Figure 19-31.
19-59