Serial Clock Signal (Scl); Serial Data Signal (Sda) - Analog Devices ADSP-BF506F Hardware Reference Manual

Interface Overview

Serial Clock Signal (SCL)

In slave mode this signal is an input and an external master is responsible
for providing the clock.
In master mode the TWI controller must set this signal to the desired fre-
quency. The TWI controller supports the standard mode of operation (up
to 100 KHz) or fast mode (up to 400 KHz).
The TWI control register (
which gives the relationship between the system clock (
controller's internally timed events. The internal time reference is derived
from using a prescaled value.
SCLK
= f
PRESCALE
The
PRESCALE
the generation of one internal time reference. The value of
be set to create an internal time reference with a period of 10 MHz. It is
represented as a 7-bit binary value.

It is not always possible to achieve 10 MHz accuracy. In such cases,
it is safe to round up the
For example, if
as 133 MHz/10 MHz = 13.3. In this case, a
ensures that all timing requirements are met.

Serial Data Signal (SDA)

This is a bidirectional signal on which serial data is transmitted or received
depending on the direction of the transfer.
16-4
TWI_CONTROL
/10MHz
SCLK
value is the number of system clock (
PRESCALE
is 133 MHz, the
SCLK
ADSP-BF50x Blackfin Processor Hardware Reference
) is used to set the
SCLK
) periods used in
SCLK
value to the next highest integer.
value is calculated
PRESCALE
PRESCALE
value
PRESCALE
) and the TWI
must
PRESCALE
value of 14