Analog Devices ADSP-BF506F Hardware Reference Manual page 691

• Receive FIFO status (
The
RCVSTAT
bytes in the receive FIFO buffer. The status is updated with each
FIFO buffer read using the peripheral data bus or write access by
the receive shift register. Simultaneous accesses are allowed.
[00] The FIFO is empty.
[01] The FIFO contains one byte of data. A single byte peripheral
read of the FIFO is allowed.
[10] Reserved
[11] The FIFO is full and contains two bytes of data. Either a sin-
gle or double byte peripheral read of the FIFO is allowed.
• Transmit FIFO status (
The
XMTSTAT
bytes in the FIFO buffer. The status is updated with each FIFO
buffer write using the peripheral data bus or read access by the
transmit shift register. Simultaneous accesses are allowed.
[00] The FIFO is empty. Either a single or double byte peripheral
write of the FIFO is allowed.
[01] The FIFO contains one byte of data. A single byte peripheral
write of the FIFO is allowed.
[10] Reserved
[11] The FIFO is full and contains two bytes of data.
ADSP-BF50x Blackfin Processor Hardware Reference
Two-Wire Interface Controller
RCVSTAT[1:0]
field is read only. It indicates the number of valid data
XMTSTAT[1:0]
field is read only. It indicates the number of valid data
)
)
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