Analog Devices ADSP-BF506F Hardware Reference Manual page 306

DMA Registers
0x7 - descriptor list (large model) mode. This mode fetches a
descriptor from memory that includes
maximum flexibility in locating descriptors in memory.
•
NDSIZE[3:0]
of descriptor elements in memory to load. This field must be 0 if in
stop or autobuffer mode. If
that extends beyond
• (data interrupt enable). This bit specifies whether to allow
DI_EN
completion of a work unit to generate a data interrupt.
•
DI_SEL
of a data interrupt—after completing the whole buffer or after
completing each row of the inner loop. This bit is used only in 2-D
DMA operation.
• (work unit transitions). This bit specifies whether the DMA
SYNC
channel performs a continuous transition (
nized transition (
information, see
In DMA transmit (memory read) and MDMA source channels, the
bit controls the interrupt timing at the end of the work unit
SYNC
and the handling of the DMA FIFO between the current and next
work unit.

Work unit transitions for MDMA streams are controlled by the
bit of the MDMA source channel's
SYNC
bit of the MDMA destination channel is reserved and must be
SYNC
0.
7-70
(flex descriptor size). This field specifies the number
, a DMA error results.
YMOD
(data interrupt timing select). This bit specifies the timing
= 1) between work units. For more
SYNC
"Work Unit Transitions" on page
ADSP-BF50x Blackfin Processor Hardware Reference
and
NDPH
and specify a descriptor
NDSIZE FLOW
SYNC
DMAx_CONFIG
, thus allowing
NDPL
= 0) or a synchro-
7-25.
register. The