Rsi Read Wait Enable Register (Rsi_Rd_Wait_En) - Analog Devices ADSP-BF506F Hardware Reference Manual

RSI Registers
Table 21-27. RSI_CONFIG Register (Cont'd)
Bit Name
6 PU_DAT3
7 PD_DAT3
15:8 Reserved

RSI Read Wait Enable Register (RSI_RD_WAIT_EN)

The
RSI_RD_WAIT_EN
issues a read wait request to an SDIO card. Once software is ready to
resume the data transfer, this bit must be cleared. The functionality
applies to both 1-bit and 4-bit SDIO modes.
RSI Read Wait Enable Register (RSI_RD_WAIT_EN)
Read/Write 1 Action/Write
15 14 13 12 11 10
0xFFC0 38CC
0
Reserved
Figure 21-25. RSI Read Wait Enable Register
21-80
Function
RSI_DATA3 pull-up enable
0 = Disable pull-up resistor on RSI_DATA3
1 = Enable pull-up resistor on RSI_DATA3
RSI_DATA3 pull-down enable
0 = Disable pull-down resistor on RSI_DATA3
1 = Enable pull-down resistor on RSI_DATA3
For more system flexibility, no internal
pull-down resistor is present. An external
pull-down resistor is required for card detection
capability on the RSI_DATA3 signal.
Reserved
register contains the
9 8 7
0 0 0 0 0 0 0 0
ADSP-BF50x Blackfin Processor Hardware Reference
bit that, when set,
SDIO_RWR
6 5 4 3 2 1 0
0 0 0 0 0 0 0
Type Default
R/W 0
R/W 0
RO 0
Reset = 0x0000
SDIO_RWR