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DMA Inner Loop Address Increment Registers (DMAx_X_MODIFY/MDMA_yy_X_MODIFY)
R/W prior to enabling channel; RO after enabling channel
15 14 13 12 11 10
X
X
Figure 7-12. DMA Inner Loop Address Increment Registers
DMA Outer Loop Count Registers
(DMAx_Y_COUNT/MDMA_yy_Y_COUNT)
For 2-D DMA, the
the outer loop count. It is not used in 1-D DMA mode. This register con-
tains the number of rows in the outer loop of a 2-D DMA sequence. For
details, see
"Two-Dimensional DMA Operation" on page
DMA Outer Loop Count Registers (DMAx_Y_COUNT/MDMA_yy_Y_COUNT)
R/W prior to enabling channel; RO after enabling channel
15 14 13 12 11 10
X
X
Figure 7-13. DMA Outer Loop Count Registers
ADSP-BF50x Blackfin Processor Hardware Reference
9
8
7
6
X
X
X
X
X
X
X
X
register, shown in
DMAx_Y_COUNT
9
8
7
6
X
X
X
X
X
X
X
X
Direct Memory Access
5
4
3
2
1
0
Reset = Undefined
X
X
X
X
X
X
X_MODIFY[15:0] (Inner
Loop Address Increment)
Stride (in bytes) to take after
each decrement of
CURR_X_COUNT
Figure
5
4
3
2
1
0
Reset = Undefined
X
X
X
X
X
X
Y_COUNT[15:0]
(Outer Loop Count)
The number of rows in
the outer loop of a 2-D
DMA sequence
7-13, contains
7-11.
7-79
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