Spi Status (Spi_Stat) Register - Analog Devices ADSP-BF506F Hardware Reference Manual

SPI Registers

SPI Status (SPI_STAT) Register

The SPI_STAT register is used to detect when an SPI transfer is complete
or if transmission/reception errors occur. The SPI_STAT register can be
read at any time.
SPI Status Register (SPI_STAT)
15 14 13 12 11 10
0 0 0
TXCOL (Transmit Collision Error) - W1C
When set, corrupt data may
have been transmitted
RXS (RX Data Buffer Status) - RO
0 - Empty
1 - Full
RBSY (Receive Error) - W1C
Set when data is received with
receive buffer full
TXS (SPI_TDBR Data Buffer Status) - RO
0 - Empty
1 - Full
Figure 18-15. SPI Status Register
Some of the bits in
that provide information only about the SPI are read-only. These bits are
set and cleared by the hardware. Sticky bits are set when an error condi-
tion occurs. These bits are set by hardware and must be cleared by
software. To clear a sticky bit, the user must write a "1" to the desired bit
position of
SPI_STAT
a "1" to bit 2 of
user to read
SPI_STAT

Sticky bits are cleared on a reset, but are not cleared on an SPI
disable.
See Figure 18-15
18-40
9 8 7 6 5
0 0 0 0 0 0 0 0
are read-only and other bits are sticky. Bits
SPI_STAT
. For example, if the
to clear the
SPI_STAT
without changing its value.
for more information.
ADSP-BF50x Blackfin Processor Hardware Reference
4 3 2 1 0
Reset = 0x0001
0 0 0 0 1
SPIF (SPI Finished) - RO
Set when SPI single word
transfer complete
MODF (Mode Fault Error) - W1C
Set in a master device when
some other device tries to
become the master
TXE (Transmission Error) - W1C
Set when transmission
occurred with no new data in
SPI_TDBR
bit is set, the user must write
TXE
error condition. This allows the
TXE