Pab Performance; Dma Access Bus (Dab), Dma Core Bus (Dcb), Dma External Bus (Deb); Dab, Dcb, And Deb Arbitration - Analog Devices ADSP-BF506F Hardware Reference Manual

• ACM
• PWM
• RSI
• DMA controller

PAB Performance

For the PAB, the primary performance criteria is latency, not throughput.
Transfer latencies for both read and write transfers on the PAB are two
cycles.
SCLK
For example, the core can transfer up to 32 bits per access to the PAB
slaves. With the core clock running at 2x the frequency of the system
clock, the first and subsequent system MMR read or write accesses take
four core clocks (
The PAB has a maximum frequency of
DMA Access Bus (DAB), DMA Core Bus (DCB), DMA
External Bus (DEB)
The DAB, DCB, and DEB buses provide a means for DMA-capable
peripherals to gain access to on-chip and off-chip memory with little or no
degradation in core bandwidth to memory.

DAB, DCB, and DEB Arbitration

Sixteen DMA channels and bus masters support the DMA-capable periph-
erals in the processor system. The twelve peripheral DMA channel
controllers can transfer data between peripherals and internal or external
memory. Both the read and write channels of the dual-stream memory
DMA controller access their descriptor lists through the DAB.
ADSP-BF50x Blackfin Processor Hardware Reference
) of latency.
CCLK
Chip Bus Hierarchy
.
SCLK
3-7