Memory; Memory Architecture - Analog Devices ADSP-BF506F Hardware Reference Manual

2 MEMORY

This chapter discusses memory population specific to the ADSP-BF50x
processors. Functional memory architecture is described in Blackfin Pro-
cessor Programming Reference.

Memory Architecture

Figure 2-1 provides an overview of the ADSP-BF50x processor system
memory map. For a detailed discussion of how to use them, see Blackfin
Processor Programming Reference.
Note the architecture does not define a separate I/O space. All resources
are mapped through the flat 32-bit address space. The memory is
byte-addressable.
The upper portion of internal memory space is allocated to the core and
system MMRs. Accesses to this area are allowed only when the processor is
in supervisor or emulation mode (see the Operating Modes and States
chapter of Blackfin Processor Programming Reference).
ADSP-BF50x Blackfin Processor Hardware Reference 2-1