Deep Sleep Operating Mode-Maximum Dynamic Power Savings; Hibernate State-Maximum Static Power Savings - Analog Devices ADSP-BF506F Hardware Reference Manual

Dynamic Power Management
Deep Sleep Operating Mode—Maximum Dynamic
Power Savings
The deep sleep mode maximizes dynamic power savings by disabling the
clocks to the processor core (CCLK) and to all synchronous peripherals
(SCLK). Asynchronous peripherals may still be running but cannot access
internal resources or external memory. Deep sleep mode can be exited
only by a hardware reset event, by a wakeup event on a programmable flag
pin (including
ble flag pin associated with the
event causes the processor to transition to active mode, and execution
resumes at the program counter value at which the processor entered deep
sleep mode. Assertion of
cessor to transition to the full on mode.
Hibernate State—Maximum Static Power Savings
The hibernate state maximizes static power savings by disabling the volt-
age and clocks to the processor core (CCLK) and to all of the peripherals
(SCLK). This setting sets the internal power supply voltage (V
0 V to provide the lowest static power dissipation. Any critical informa-
tion stored internally (for example, memory contents, register contents,
and other information) must be written to a non-volatile storage device
prior to removing power if the processor state is to be preserved. Writing 0
to the
HIBERNATEB
used to signal an external voltage regulator to shut down.
Since V
DDEXT
three-state, unless otherwise specified. This allows other devices that may
be connected to the processor to still have power applied without drawing
unwanted current.
The processor can be woken up by asserting the
wakeup events initiate the hardware reset sequence. Individual sources are
1-26
, , or ), or by a wakeup event on the programma-
PH0 PF8 PF9
CAN_RX
while in deep sleep mode causes the pro-
RESET
bit causes
EXT_WAKE
can still be supplied in this mode, all of the external pins
ADSP-BF50x Blackfin Processor Hardware Reference
signal ( ). A programmable flag
PG1
to transition low, which can be
pin. All hibernate
RESET
) to
DDINT