Configuring The Ebiu For Synchronous Read Mode - Analog Devices ADSP-BF506F Hardware Reference Manual

• through
CR2
• The value to be programmed in the X latency bit field (
through
Table 6-31.
Table 6-31. X Latency Setting Depends on Frequency
NOR_CLK Frequency
 30 MHz


40 MHz


50 MHz

Configuring the EBIU for Synchronous Read Mode

In order to support internal flash operation in synchronous burst mode,
the EBIU has to be configured in synchronous burst mode by program-
ming the
B0MODE
selecting the appropriate
register, and configuring the
EBIU_FCTL
•
B0RDYEN
mode.
•
B0RDYPOL
ter (
CR10
flash configuration register (
• must be set to
BOTT
ADSP-BF50x Blackfin Processor Hardware Reference
have to be programmed to
CR0
) depends on the
CR11
X Latency (in Terms of NOR_CLK Cycles)
2


3


4
field in the
EBIU_MODECTL
NOR_CLK
must be programmed to 1 for synchronous burst read
must be set to 1 if bit 10 of the flash configuration regis-
) is programmed to 0 and programmed to 0 if bit 10 of the
.
b#11
Internal Flash Memory
b#011
frequency, as shown in
NOR_CLK
register to the value
frequency in the
BCLK
EBIU_AMBCTL
) is set to 1.
CR10
.
CR13
,
b#11
bit field of the
register as follows:
6-85