Analog Devices ADSP-BF506F Hardware Reference Manual page 239

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SDRAM and SRAM are not available on all products. Refer to
"Unique Information for the ADSP-BF50x Processor" on
page 7-103
DMA transfers on the processor can be descriptor-based or register-based.
Register-based DMA allows the processor to directly program DMA con-
trol registers to initiate a DMA transfer. On completion, the control
registers may be automatically updated with their original setup values for
continuous transfer, if needed.
Descriptor-based DMA transfers require a set of parameters stored within
memory to initiate a DMA sequence. This sort of transfer allows the
chaining together of multiple DMA sequences. In descriptor-based DMA
operations, a DMA channel can be programmed to automatically set up
and start another DMA transfer after the current sequence completes.
Examples of DMA styles supported by flex descriptors include:
• A single linear buffer that stops on completion (
• A linear buffer with byte strides of any integer value, including
negative values (
• A circular, auto-refreshing buffer that interrupts on each full buffer
• A similar buffer that interrupts on fractional buffers (for example,
½, ¼) (2-D DMA)
• 1-D DMA, using a set of identical ping-pong buffers defined by a
linked ring of 3-word descriptors, each containing a link pointer
and a 32-bit address
• 1-D DMA, using a linked list of 5-word descriptors containing a
link pointer, a 32-bit address, the buffer length, and a
configuration
ADSP-BF50x Blackfin Processor Hardware Reference
to determine whether it applies to this product.
DMAx_X_MODIFY
Direct Memory Access
FLOW
register)
= stop mode)
7-3