Analog Devices ADSP-BF506F Hardware Reference Manual page 864

Interface Overview
TX REGISTER
TX FIFO
4 x 32 OR 8 x 16
TX PRI
HOLD REG HOLD REG
COMPANDING
HARDWARE
TX PRI
SHIFT REG SHIFT REG
DTPRI DTSEC
Figure 19-1. SPORT Block Diagram
1 All wide arrow data paths are 16- or 32-bits wide, depending on SLEN. for SLEN = 2 to 15, a 16-bit
data path with 8-deep fifo is used. for SLEN = 16 to 31, a 32-bit data path with 4-deep fifo is used.
2 TX register is the bottom of the TX fifo, RX register is the top of the RX fifo.
3 In multichannel mode, the TFS pin acts as transmit data valid (TDV). For more information, see
"Multichannel Operation" on page
A SPORT receives serial data on its
serial data on its
simultaneously for full-duplex operation. For transmit, the data bits
( and
DTPRI DTSEC
receive, the data bits (
clock ( ). The serial clock is an output if the processor generates it, or
RSCLK
an input if the clock is externally generated. Frame synchronization signals
and are used to indicate the start of a serial data word or stream of
RFS TFS
serial words.
19-6
TX SEC
CONTROL
INTERNAL
GENERATOR
TX SEC
TFS TSCLK
19-15.
and
DTPRI DTSEC
) are synchronous to the transmit clock (
and
DRPRI
ADSP-BF50x Blackfin Processor Hardware Reference
PAB
DAB
SERIAL
CLOCK
RSCLK RFS
1, 2, 3
and
DRPRI DRSEC
outputs. It can receive and transmit
) are synchronous to the receive
DRSEC
RX REGISTER
RX FIFO
4 x 32 OR 8 x 16
RX PRI RX SEC
HOLD REG HOLD REG
COMPANDING
HARDWARE
RX PRI RX SEC
SHIFT REG SHIFT REG
DRPRI DRSEC
inputs and transmits
). For
TSCLK