Analog Devices ADSP-BF506F Hardware Reference Manual page 534

Programming Examples
| nCUDINV
| nCDGINV
| nDEBE
| nCNTE (z);
w[P5] = R5;
/* Zero the CNT_COUNT, CNT_MIN and CNT_MAX registers
This is optional as after reset they are default to zero */
P5.H = hi(CNT_COMMAND);
P5.L = lo(CNT_COMMAND);
R5 = W1LCNT_ZERO | W1LMIN_ZERO | W1LMAX_ZERO (z);
w[P5] = R5;
/* Clear any identified interrupts */
P5.H = hi(CNT_STATUS);
P5.L = lo(CNT_STATUS);
R5.L = ICII
*/
| UCII
| DCII
| MINCII /* Min Count Interrupt Identifier */
| MAXCII /* Max Count Interrupt Identifier */
| COV31II /* Bit 31 Overflow Interrupt Identifier */
| COV15II /* Bit 15 Overflow Interrupt Identifier */
| CZEROII /* Count to Zero Interrupt Identifier */
| CZMII
| CZMEII /* CZM Error Interrupt Identifier */
| CZMZII; /* CZM Zeroes Counter Interrupt Identifier */
w[P5] = R5;
Listing 13-2 illustrates how to set up the peripheral and core interrupts for
the GP counter. This example assumes the counter interrupts are gener-
ated on IRQ27, which is assumed to be mapped to the IVG11 interrupt.
Finally, the system and peripheral interrupts are unmasked, and then the
13-28
/* Polarity of CUD pin */
/* Polarity of CDG Pin */
/* Disable the debounce */
/* Disable the counter */
/* Illegal Gray/Binary Code Interrupt Identifier
/* Up count Interrupt Identifier */
/* Down count Interrupt Identifier */
/* CZM Pin Interrupt Identifier */
ADSP-BF50x Blackfin Processor Hardware Reference