Analog Devices ADSP-BF506F Hardware Reference Manual page 814

Interface Overview
Figure 18-4 shows one processor as a master with three processors (or
other SPI-compatible devices) as slaves.
SLAVE DEVICE
MISO SCK MOSI
Figure 18-4. Single-Master, Multiple-Slave Configuration
The transmit buffer becomes full after it is written to. It becomes empty
when a transfer begins and the transmit value is loaded into the shift regis-
ter. The receive buffer becomes full at the end of a transfer when the shift
register value is loaded into the receive buffer. It becomes empty when the
receive buffer is read.

The
SPIF
disabled.
Upon entering DMA mode, the transmit buffer and the receive
buffer become empty. That is, the
SPI_STAT
18-10
SLAVE DEVICE
SPISS
MISO SCK
bit in the
SPI_STAT
register are initially cleared upon entering DMA mode.
ADSP-BF50x Blackfin Processor Hardware Reference
SLAVE DEVICE
SPISS
MOSI MISO SCK
MISO SCK MOSI
PF/PG/PH
MASTER
PF/PG/PH
DEVICE
register is set when the SPI port is
bit and the
TXS
SPISS
MOSI
VDD
SPISS
PF/PG/PH
bit in the
RXS