Table of Contents
Advertisement
Core Timer Scale Register (TSCALE)
The TSCALE register is shown in
ing value that is one less than the number of cycles between decrements of
TCOUNT. For example, if the value in the TSCALE register is 0, the
counter register decrements once every CCLK clock cycle. If TSCALE is
1, the counter decrements once every two cycles.
Core Timer Scale Register (TSCALE)
31 30 29 28 27 26
X
X
15 14 13 12 11 10
X
X
Figure 11-5. Core Timer Scale Register
Programming Examples
Listing 11-1
configures the core timer in auto-reload mode. Assuming a
of 500 MHz, the resulting period is 1 second. The initial period is
CCLK
twice as long as the others.
Listing 11-1. Core Timer Configuration
#include <defBF527.h>/*ADSP-BF527 product is used as an example*/
.section L1_code;
.global _main;
_main:
/* Register service routine at EVT6 and unmask interrupt */
p1.l = lo(IMASK);
p1.h = hi(IMASK);
ADSP-BF50x Blackfin Processor Hardware Reference
25 24 23 22 21 20 19 18 17 16
X
X
X
X
X
X
X
X
9
8
7
6
X
X
X
X
X
X
X
X
Figure
11-5. The register stores the scal-
Reset = Undefined
X
X
X
X
X
X
5
4
3
2
1
0
X
X
X
X
X
X
Scale Value[7:0]
Core Timer
11-7
Advertisement
Table of Contents
Need help?
Do you have a question about the ADSP-BF506F and is the answer not in the manual?