Using Core - Analog Devices ADSP-BF506F Hardware Reference Manual

Programming Model

If the core is being used to read the receive FIFO, it is advised not
to pend on the
driven on the
bit of the command. At minimum, an additional 48
will pass before the response is received, during which time the
receive buffer may potentially have received 24 bytes of data on a
4-bit bus and will be approaching the half full state. Software
should ensure that the receive buffer does not become full prior to
data being read from the receive FIFO.

Using Core

The procedure is as follows:
1. Write the
RCA should be written to the upper 16-bits of the
register.
2. Write the
command, configuring the command path state machine to expect
a short response by setting
response type is R1b.
3. Wait for the
register and clear the status bit once detected via the
register.
4. Ensure that the device is not busy and no errors occurred by
verifying the response contained in
5. Write the number of bytes to be transferred to the
register. This will be 512 bytes for a single block.
6. Write the appropriate timeout value for a read operation to the
RSI_DATA_TIMER
21-40
CMD_RESP_END
signals two
RSI_DATAx
register with the cards RCA. The 16-bit
RSI_ARGUMENT
register with the
RSI_COMMAND
CMD_RESP
indication within the
CMD_RESP_END
register.
ADSP-BF50x Blackfin Processor Hardware Reference
flag. It is possible for data to be
cycles after the end
RSI_CLK
SELECT/DESELECT_CARD
and clearing
RSI_RESPONSE0
cycles
RSI_CLK
RSI_ARGUMENT
. The
CMD_L_RESP
RSI_STATUS
RSI_STATUSCL
.
RSI_DATA_LGTH